PROCESSOR SYSTEM AND ACCELERATOR

• US 20140304491A1
• Filed: 10/30/2012
• Published: 10/09/2014
• Est. Priority Date: 11/04/2011
• Status: Active Grant

• Current Assignee: Waseda University (Waseda University Educational Association)
• Original Assignee: Waseda University (Waseda University Educational Association)
• Inventors: Kasahara, Hironori, Kimura, Keiji
• Granted Patent: US 9,846,673 B2
• Time in Patent Office: Days
• US Class Current: 712/42
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3881 Arrangements for communication of instructions and data
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

It is provided a processor system comprising at least one processor core including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes read instruction in a case where the read instruction is a flag checking instruction and a flag indicating the completion of predetermined processing has been written; and stores the data subjected to the acceleration processing after completion of the acceleration processing, and further writes a flag indicating the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, read instruction corresponding to a flag in a case where the read instruction is the flag checking instruction and it is confirmed that the flag indicating the completion of the acceleration processing has been written.

Claims

1. A processor system comprising:

at least one processor core provided on a semiconductor chip and including;

a processor for performing arithmetic processing;

a memory; and

an accelerator coupled to the processor and the memory through a coupling network;

wherein;

the memory includes;

an instruction area for storing a task executed by the processor and the accelerator in advance;

a synchronization flag area for storing a flag used to synchronize an operation of the processor and an operation of the accelerator therebetween; and

a data area for storing data to be processed by the processor and the accelerator and the processed data;

the accelerator is configured to;

read an instruction included in the task to be executed by the accelerator which is stored in the instruction area when the processor system is booted;

operate in accordance with the read instruction;

start, even if the processor is executing another processing, acceleration processing by reading the data written in the data area and execute the read instruction corresponding to a flag in a case where the read instruction is a flag checking instruction and it is confirmed by the flag checking instruction that the flag indicating that the processor has completed predetermined processing has been written into the synchronization flag area; and

store the data subjected to the acceleration processing into the data area by the instruction read by the accelerator after completion of the acceleration processing, and further write a flag indicating that the completion of the acceleration processing into the synchronization flag area by a flag setting instruction read by the accelerator; and

the processor is configured to;

read the instruction included in the task executed by the processor which is stored in the instruction area when the processor system is booted;

operate in accordance with the read instruction;

start, even if the accelerator is executing another processing, the read instruction corresponding to a flag in a case where the read instruction is a flag checking instruction and it is confirmed by the flag checking instruction that the flag indicating the completion of the acceleration processing has been written into the synchronization flag area.

2. The processor system according to claim 1, wherein:

each of the accelerator and the processor is configured to write a plurality of different flags corresponding to the instructions to be executed subsequently into the synchronization flag area in accordance with progress of processing executed by itself; and

each of the accelerator and the processor for subsequently executing the instructions is configured to confirm the flag written in the synchronization flag area and execute the corresponding instruction.

3. The processor system according to claim 1, wherein:

the memory includes at least one of a local memory that is accessible by the accelerator and the processor, or a distributed shared memory that is also accessible by another processor core;

the at least one processor core further includes a data transfer unit for transferring data between the memories;

the synchronization flag area includes an area for storing a flag used to synchronize an operation of the data transfer unit and operations of the processor and the accelerator therebetween;

the instruction area includes an area for storing the task executed by the data transfer unit in advance;

the accelerator is configured to;

start, even if the data transfer unit is executing another data transfer processing, the acceleration processing by reading the data written in the data area and execute the instruction corresponding to the flag in a case of confirming that a flag indicating that the data transfer unit has completed predetermined data transfer processing has been written into the synchronization flag area; and

store the data subjected to the acceleration processing into the data area after the completion of the acceleration processing, and further write the flag indicating the completion of the acceleration processing into the synchronization flag area; and

the data transfer unit is configured to start, even if the accelerator is executing another processing, the data transfer processing by executing the instruction corresponding to the flag in a case of confirming that the flag indicating the completion of the acceleration processing has been written into the synchronization flag area.

6. The processor system according to claim 1, wherein:

the accelerator includes;

a processing part for executing the acceleration processing;

an internal storage area for temporarily storing data processed by the processing part; and

a load/store unit for executing data transfer between the internal storage area and the memory; and

the load/store unit includes a load/store-unit-side flag writing/confirming unit for writing the flag into the synchronization flag area in accordance with an execution status of the data transfer between the internal storage area and the memory and confirming that the flag has been written into the synchronization flag area.

7. The processor system according to claim 1, wherein:

the accelerator includes;

a processing part for executing the acceleration processing; and

an internal storage area for temporarily storing data processed by the processing part; and

the processing part includes a processing-part-side flag writing/confirming unit for writing the flag into the synchronization flag area in accordance with an execution status of data transfer between the internal storage area and the processing part and confirming that the flag has been written into the synchronization flag area.

8. The processor system according to claim 1, wherein:

the accelerator includes;

a processing part for executing the acceleration processing;

an internal storage area for temporarily storing data processed by the processing part; and

a load/store unit for executing data transfer between the internal storage area and the memory;

the processing part includes a processing-part-side flag writing/confirming unit for writing the flag into the synchronization flag area in accordance with an execution status of processing performed by the processing part and confirming that the flag has been written into the synchronization flag area; and

the load/store unit includes a load/store-unit-side flag writing/confirming unit for writing the flag into the synchronization flag area in accordance with the execution status of processing performed by the load/store unit and confirming that the flag has been written into the synchronization flag area.

9. The processor system according to claim 1, wherein:

the accelerator includes;

a processing part for executing the acceleration processing;

an internal storage area for temporarily storing data processed by the processing part;

a load/store unit for executing data transfer between the internal storage area and the memory; and

a flag exchange register for storing a flag used to synchronize an operation of the processing part and an operation of the load/store unit;

the processing part includes a processing-part-side flag writing/confirming unit for writing the flag into one of the synchronization flag area and the flag exchange register in accordance with an execution status of processing performed by the processing part and confirming that the flag has been written into the one of the synchronization flag area and the flag exchange register; and

the load/store unit includes a load/store-unit-side flag writing/confirming unit for writing the flag into one of the synchronization flag area and the flag exchange register in accordance with the execution status of processing performed by the load/store unit and confirming that the flag has been written into the one of the synchronization flag area and the flag exchange register.

10. The processor system according to claim 1, wherein the processor system includes a plurality of the processor cores.

11. The processor system according to claim 10, further comprising at least one of an on-chip centralized shared memory provided on the semiconductor chip shared by the plurality of the processor cores or an off-chip centralized shared memory provided outside the semiconductor chip which is shared by the plurality of the processor cores.

13. The processor system according to claim 3, wherein:

the memory further includes at least one of a memory or a register provided inside the accelerator; and

the data transfer unit is configured to;

store, even if one of the processor and the accelerator is executing another processing, calculation result data obtained from the accelerator in the acceleration processing from the accelerator into the memory in a case of confirming that a flag indicating the completion of the acceleration processing has been written into the synchronization flag area;

execute load processing for previously reading data to be used in a next round of the acceleration processing performed by the accelerator from the memory into the accelerator even if one of the processor and the accelerator is executing another processing; and

write a flag indicating that the load processing has been completed into the synchronization flag area.

4. A processor system comprising:

at least one processor core provided on a semiconductor chip and including as components;

a processor for performing arithmetic processing;

memories;

a data transfer unit for transferring data between the memories; and

an accelerator coupled to the processor, the memories and the data transfer unit through a coupling network;

wherein

the memories include;

an instruction area for storing a task executed by each of the respective components including the processor, the data transfer unit, and the accelerator in advance;

a synchronization flag area for storing a flag used to synchronize respective operations of the respective components therebetween; and

a data area for storing data to be processed by the respective components and the processed data; and

the respective components are each configured to read the instruction included in the tasks corresponding to the respective components stored in the instruction area when the processor system is booted, and operate in accordance with the read instruction; and

a first component of the components is configured to complete predetermined processing according to the instruction read, store the processed data into the data area, and further write a flag indicating the completion of the predetermined processing into the synchronization flag area in accordance with the tasks corresponding to the component; and

a second component other than the first component is configured to start, even if a component other than the second component is executing another processing, execution of the instruction read by the second component corresponding to a flag by reading the processed data stored in the data area in a case of confirming that the flag has been written by the instruction read by the second component, store the data subjected to the execution of the instruction into the data area after completion of the execution of the instruction, and further write a flag indicating the completion of the instruction into the synchronization flag area in accordance with the tasks corresponding to the component.

5. The processor system according to claim 4, wherein:

the instructions executed by the respective components including the processor, the accelerator, and the data transfer unit are generated from a program to be executed in the processor system with reference to information obtained by analyzing the program; and

the generated instruction is associated with the flag.

22. The processor system according to claim 4, wherein:

the memory further includes at least one of a memory or a register provided inside the accelerator; and

the data transfer unit is configured to;

store, even if one of the processor and the accelerator is executing another processing, calculation result data obtained from the accelerator in the acceleration processing from the accelerator into the memory in a case of confirming that a flag indicating the completion of the acceleration processing has been written into the synchronization flag area;

execute load processing for previously reading data to be used in a next round of the acceleration processing performed by the accelerator from the memory into the accelerator even if one of the processor and the accelerator is executing another processing; and

write a flag indicating that the load processing has been completed into the synchronization flag area.

12. (canceled)

14. An accelerator, which is included in a processor system including a processor for performing arithmetic processing and a memory for storing data, the accelerator being coupled to the processor and the memory through a coupling network,

the memory including:

an instruction area for storing a task executed by the processor and the accelerator in advance;

a synchronization flag area for storing a flag used to synchronize an operation of the processor and an operation of the accelerator therebetween; and

a data area for storing data to be processed by the processor and the accelerator and the processed data,

the accelerator comprising;

a processing part for executing acceleration processing; and

an internal storage area for temporarily storing data processed by the processing part, wherein;

the accelerator is configured to;

read an instruction included in the task to be executed by the accelerator which is stored in the instruction area when the processor system is booted;

operate in accordance with the read instruction;

start, even if the processor is executing another processing, the acceleration processing by executing the read instruction corresponding to a flag by the processing part in a case where the read instruction is a flag checking instruction and it is confirmed that the flag indicating that the processor has completed predetermined processing has been written into the synchronization flag area; and

write calculation result data obtained in the acceleration processing into the internal storage area, and write a flag indicating the completion of the acceleration processing into the synchronization flag area by the read instruction after the acceleration processing has been completed.

15. The accelerator according to claim 14, wherein:

the tasks executed by the processor and the accelerator are generated from a program to be executed in the processor system with reference to information obtained by analyzing the program; and

the generated instruction is associated with the flag.

16. The accelerator according to claim 14, wherein the accelerator is configured to write a plurality of different flags corresponding to the instructions to be executed subsequently into the synchronization flag area in accordance with progress of processing executed by itself.

18. The accelerator according to claim 14, further comprising a load/store unit for executing data transfer between the internal storage area and the memory,

wherein the load/store unit includes a load/store-unit-side flag writing/confirming unit for writing the flag into the synchronization flag area in accordance with an execution status of the data transfer between the internal storage area and the memory and confirming that the flag has been written into the synchronization flag area.

19. The accelerator according to claim 18, wherein the processing part includes a processing-part-side flag writing/confirming unit for writing the flag into the synchronization flag area in accordance with an execution status of processing performed by the processing part and confirming that the flag has been written into the synchronization flag area.

20. The accelerator according to claim 19, further comprising a flag exchange register for storing a flag used to synchronize an operation of the processing part and an operation of the load/store unit, wherein:

the processing-part-side flag writing/confirming unit is configured to write the flag into the flag exchange register in accordance with the execution status of the processing performed by the processing part, and to confirm that the flag has been written into the flag exchange register; and

the load/store-unit-side flag writing/confirming unit is configured to write the flag into the flag exchange register in accordance with the execution status of the processing performed by the load/store unit, and to confirm that the flag has been written into the flag exchange register.

21. The accelerator according to claim 14, wherein the processing part includes a processing-part-side flag writing/confirming unit for writing the flag into the synchronization flag area in accordance with an execution status of data transfer between the internal storage area and the processing part and confirming that the flag has been written into the synchronization flag area.

17. (canceled)