SELF-ALIGNED STRUCTURE FOR BULK FinFET

• US 20140306274A1
• Filed: 08/30/2013
• Published: 10/16/2014
• Est. Priority Date: 04/11/2013
• Status: Abandoned Application

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Basker, Veeraraghavan S., Leobandung, Effendi, Yamashita, Tenko, Yeh, Chun-Chen
• Application Number:
  US14/015,967
• Publication Number:
  US 20140306274A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A FinFET structure which includes a bulk semiconductor substrate; semiconductor fins extending from the bulk semiconductor substrate, each of the semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is undoped; a portion of the bulk semiconductor substrate directly underneath the plurality of semiconductor fins being doped to form an n+ or p+ well; and an oxide formed between the bottom portions of the fins.

Claims

1. A FinFET structure comprising:

a bulk semiconductor substrate;

a plurality of semiconductor fins extending from the bulk semiconductor substrate, each of the plurality of semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is undoped;

a portion of the bulk semiconductor substrate directly underneath the plurality of semiconductor fins being doped to form an n+ or p+ well; and

an oxide formed between the bottom portions of the fins.

2. The FinFET structure of claim 1 wherein the bottom portion of each of the plurality of semiconductor fins is thinned compared to the top portion of the plurality of semiconductor fins.

3. The FinFET structure of claim 2 wherein a parasitic capacitance of the FinFET structure is reduced due to the thinned bottom portion of each of the plurality of semiconductor fins.

4. The FinFET structure of claim 1 wherein the semiconductor fins and bulk semiconductor substrate are silicon.

5. The FinFET structure of claim 1 further comprising a gate that wraps around at least one of the semiconductor fins.

6. The FinFET structure of claim 1 wherein each of the plurality of semiconductor fins has a source and a drain and wherein the well blocks the electrical path between the source and drain and minimizes junction leakage current.

7. The FinFET structure of claim 1 wherein the oxide is only in contact with the bulk semiconductor substrate and the bottom portions of the fins.

8. The FinFET structure of claim 1 wherein the oxide is only in contact with the doped portion of the bulk semiconductor substrate and the doped portion of the fins.