ESD PROTECTION CIRCUIT

• US 20140307354A1
• Filed: 02/05/2014
• Published: 10/16/2014
• Est. Priority Date: 04/16/2013
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: WATANABE, Kentaro
• Application Number:
  US14/173,342
• Publication Number:
  US 20140307354A1
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0285 bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits H01L27/0281 takes precedence
• CPC Class Codes: H02H 9/041 using a short-circuiting device
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

An ESD protection circuit includes an RC circuit connected between a first power terminal to which an external power voltage is to be applied, a second power terminal to which a ground potential is to be applied, and an internal power supply line connected to a third power terminal. A switch transistor having a main current channel is connected between the first power terminal and the internal power supply line, and a shunt transistor having a main current channel is connected between the second power terminal and the internal power supply line. A trigger signal that is based on an output of the RC circuit is supplied to a control electrode of the shunt transistor through a drive circuit.

Claims

1. An ESD protection circuit comprising:

a first power terminal to which an external power voltage is to be applied;

a second power terminal to which a ground potential is to be applied;

an internal power supply line;

an RC circuit including a resistor and a capacitor connected in series between the first power terminal and the second power terminal;

a common node to which the resistor and the capacitor are connected; and

a switch transistor having a main current channel connected between the first power terminal and the internal power supply line;

a shunt transistor having a main current channel connected between the second power terminal and the internal power supply line;

a drive circuit which supplies a trigger signal to a control electrode of the shunt transistor in accordance with a potential of the common node.

2. The circuit according to claim 1, wherein

the internal power supply line is connected to a third power terminal.

3. The circuit according to claim 1, wherein

a signal based on a comparison result between a feedback voltage of the internal power supply line and a predetermined reference voltage is supplied to the control electrode of the switch transistor.

4. The circuit according to claim 1, wherein

the shunt transistor is an NMOS transistor having source and back gate electrodes that are connected to the second power terminal, a drain electrode connected to the internal power supply line, and a gate electrode which a trigger signal of the first drive circuit is supplied to.

5. The circuit according to claim 1, wherein

the switch transistor is a PMOS transistor having source and back gate electrodes connected to the first power terminal, and a drain electrode connected to the internal power supply line.

6. The circuit according to claim 1, wherein

the drive circuit includes at least one stage of an inverter circuit.

7. The circuit according to claim 1, further comprising:

a first ESD protection diode connected between the first power terminal and the internal power supply line; and

a second ESD protection diode connected between the second power terminal and the internal power supply line.

8. The circuit according to claim 7, wherein

the first ESD protection diode is formed as a parasitic diode of the switch transistor.

9. The circuit according to claim 1, wherein

the resistor of the RC circuit has a first end connected to the first power terminal and a second end connected to the common node and the capacitor of the RC circuit has a first end connected to the common node and a second end connected to the second power terminal.

10. The circuit according to claim 9, wherein

the drive circuit includes three inverter circuits connected in series, the last inverter circuit connected in series producing an output signal that is the trigger signal supplied to the control electrode of the shunt transistor.

11. The circuit according to claim 1, wherein

the capacitor of the RC circuit has a first end connected to the first power terminal and a second end connected to the common node and the resistor of the RC circuit has a first end connected to the common node and a second end connected to the second power terminal.

12. The circuit according to claim 11, wherein

the drive circuit includes first and second inverter circuits, the second inverter circuit producing an output signal that is the trigger signal supplied to the control electrode of the shunt transistor.

13. An ESD protection circuit in a semiconductor device including a first power terminal to which an external power voltage is to be applied, a second power terminal to which a ground potential is to be applied, an internal power supply line, a switch transistor having a main current channel connected between the first power terminal and the internal power supply line, and an internal load circuit biased by a voltage of the internal power supply line, the ESD protection circuit comprising:

a shunt transistor having a main current channel connected between the second power terminal and the internal power supply line; and

an RC circuit, connected between the first power terminal and the second power terminal, which outputs a signal for controlling conductivity of the shunt transistor.

14. The circuit according to claim 13, further comprising:

a drive circuit including at least one stage of inverter, which supplies a trigger signal to a control electrode of the shunt transistor in response to an output signal of the RC circuit.

15. The circuit according to claim 14, wherein

the resistor of the RC circuit has a first end connected to the first power terminal and a second end connected to an input of the drive circuit and the capacitor of the RC circuit has a first end connected to the input of the drive circuit and a second end connected to the second power terminal.

16. The circuit according to claim 15, wherein

the drive circuit includes three inverter circuits connected in series, the last inverter circuit connected in series producing an output signal that is the trigger signal supplied to the control electrode of the shunt transistor.

17. The circuit according to claim 14, wherein

the capacitor of the RC circuit has a first end connected to the first power terminal and a second end connected to an input of the drive circuit and the resistor of the RC circuit has a first end connected to the input of the drive circuit and a second end connected to the second power terminal.

18. The circuit according to claim 17, wherein

the drive circuit includes the first and second inverter circuits connected in series, the second inverter circuit producing an output signal that is the trigger signal supplied to the control electrode of the shunt transistor.

19. A method of driving a shunt transistor of an ESD protection circuit having a first power terminal to which an external power voltage is to be applied, a second power terminal to which a ground potential is to be applied, an internal power supply line, and an RC circuit including a resistor and a capacitor connected in series between the first power terminal and the second power terminal, wherein the shunt transistor includes a main current channel connected between the second power terminal and the internal power supply line, said method comprising:

supplying an input signal into an inverter from a common node between the resistor of the RC circuit and the capacitor of the RC circuit; and

generating a trigger signal that is supplied to a control electrode of the shunt transistor from the output signal of the inverter.

20. The method according to claim 19, further comprising:

generating a control signal based on a comparison of a feedback voltage of the internal power supply line and a predetermined reference voltage; and

supplying the control signal to a control electrode of a switch transistor that is connected between the first power terminal and the internal power supply line.