Systems and Methods for Faster Throughput for Compressed Video Data Decoding

• US 20140307793A1
• Filed: 09/05/2007
• Published: 10/16/2014
• Est. Priority Date: 09/06/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander
• Granted Patent: US 9,094,686 B2
• Time in Patent Office: Days
• US Class Current: 375/240.16
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder

Abstract

Presented herein are system(s) and method(s) for faster throughput for video decoding. In one embodiment, there is presented a pixel reconstructor for generating reconstructed pixels. The pixel reconstructor comprises a SIMD processor, a data access unit, and a circuit. The SIMD processor applies at least one prediction error to at least one block of prediction pixels. The data access unit provides the at least one prediction error and the at least one block of prediction pixels. A circuit determines whether two or more prediction errors and two or more prediction pixels can be concurrently processed by the SIMD processor.

Claims

1. A pixel reconstructor for generating reconstructed pixels, said pixel reconstructor comprising:

a SIMD processor for applying at least one prediction error to at least one block of prediction pixels; and

a data access unit for providing the at least one prediction error and the at least one block of prediction pixels; and

a circuit for determining whether two or more prediction errors and two or more prediction pixels can be concurrently processed by the SIMD processor.

2. The pixel reconstructor of claim 1, wherein the SIMD processor comprises:

an instruction memory for storing a set of instructions; and

a plurality of processing elements for concurrently executing the set of instructions for a corresponding plurality of pixels from a row in the at least one prediction error and a corresponding plurality of pixels from a row in the at least one block of prediction pixels.

3. The pixel reconstructor of claim 2, wherein the plurality of processing elements comprises at least 16 processing elements.

4. A motion compensator for generating prediction pixels, said motion compensator comprising:

a SIMD processor for processing one or more blocks of pixels associated with at least one partition; and

a data access unit for providing the one or more blocks of pixels; and

a circuit for determining whether one or more blocks associated with two or more partitions can be concurrently processed by the SIMD processor.

5. The motion compensator of claim 4, wherein the SIMD processor comprises:

an instruction memory for storing a set of instructions; and

a plurality of processing elements for concurrently executing the set of instructions for a corresponding plurality of pixels from a row in the one or more blocks associated with the at least one partition.

6. The motion compensator of claim 5, wherein the plurality of processing elements comprises at least 19 processing elements.

7. The motion compensator of claim 4, wherein processing one or more blocks associated with at least one partition comprises interpolating reference pixels from the one or more blocks.

8. The motion compensator of claim 4, wherein processing one or more blocks associated with at least one partition comprises applying a first weight to a first one of the one or more blocks and a second weight to a second one of the one or more blocks.

9. The motion compensator of claim 4, further comprising:

a direct memory access unit for fetching a plurality of words from a memory, wherein the plurality of words comprise the one or more blocks of pixels and additional pixels.

10. The motion compensator of claim 9, wherein the data access unit selects at least a portion of the one or more blocks of pixels from the words from the memory.

11. A method for generating reconstructed pixels, said method comprising:

determining whether two or more prediction errors and two or more prediction pixels can be concurrently processed;

if the two or more prediction errors and the two or more prediction pixels can be concurrently processed;

consolidating the two or more prediction errors and the two or more prediction pixels;

concurrently applying the two or more prediction errors to the two or more prediction pixels.

12. The method of claim 11, wherein concurrently applying the two or more prediction errors to the two or more prediction pixels further comprises:

concurrently executing a set of instructions for a plurality of pixels from a row in the at least one prediction error and a corresponding plurality of pixels from a row in the at least one block of prediction pixels.

13. The method of claim 12, wherein the plurality of pixels from the row in the at least one prediction error comprises 16 pixels.

14. A method for generating prediction pixels, said method comprising:

determining whether a first block of prediction pixels and a second block of prediction pixels can be concurrently generated from a first one or more blocks of pixels associated with a first partition and a second one or more blocks associated with a second partition;

if the first block of prediction pixels and the second block of prediction pixels can be concurrently generated;

consolidating the first one or more blocks and the second one or more blocks; and

concurrently processing the first one or more blocks and the second one or more blocks.

15. The method of claim 14, wherein concurrently processing the first one or more blocks further comprises:

concurrently processing a plurality of pixels from a row in the first one or more blocks and a plurality of pixels from a row in the second one or more blocks.

16. The method of claim 15, wherein the plurality of pixels in the row of the first block comprise at least 19 pixels.

17. The method of claim 14, wherein processing further comprises interpolating.

18. The method of claim 14, wherein processing one or more blocks associated with at least one partition comprises processing two or more blocks.

19. The method of claim 14, further comprising:

fetching a plurality of words from a memory, wherein the plurality of words comprise the one or more blocks of pixels and additional pixels.

20. The method of claim 19, further comprising selecting the one or more blocks of pixels from the words from the memory.