HYBRID INTEGRATION OF GROUP III-V SEMICONDUCTOR DEVICES ON SILICON

• US 20140307997A1
• Filed: 12/20/2011
• Published: 10/16/2014
• Est. Priority Date: 12/20/2011
• Status: Active Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bar, Hanan, Heck, John, Feshali, Avi, Feldesh, Ran
• Application Number:
  US13/976,913
• Publication Number:
  US 20140307997A1
• Time in Patent Office: Days
• US Class Current: 385/14
• CPC Class Codes: G02B 2006/12061 Silicon
• CPC Class Codes: G02B 6/12004 Combinations of two or more optical elements
• CPC Class Codes: G02B 6/1225 comprising photonic band-gap structures or photonic lattices
• CPC Class Codes: G02B 6/13 Integrated optical circuits characterised by the manufacturing method
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions

Abstract

Photonic passivation layers, III-V semiconductor die with offcut edges, and NiGe contact metallization for silicon-based photonic integrated circuits (PICs). In embodiments, a non-sacrificial passivation layer is formed on a silicon photonic element, such as a waveguide for protection of the waveguide surfaces. In embodiments, a III-V semiconductor film is transferred from a III-V growth substrate that is singulated along streets that are misaligned from cleave planes to avoid crystallographic etch artifacts in a layer transfer process. In embodiments, a NiGe contact metallization is employed for both p-type and n-type contacts on a device formed in the transferred III-V semiconductor layer to provide low specific contact resistance and compatibility with MOS processes.

Claims

1. A photonic integrated circuit (PIC), comprising:

photonic element comprising silicon disposed on a substrate;

a photonic passivation layer (PPL) comprising a nitrogen-doped silicon oxide having a thickness of less than 100 Å

disposed on the photonic element; and

an interlayer dielectric (ILD) disposed on the PPL.

2. The PIC of claim 1, wherein the PPL has a thickness between 5 Å

and 15 Å

.

3. The PIC of claim 1, wherein the PPL has a concentration of nitrogen atoms between 10¹² and 10¹⁶ atoms/cm³.

4. The PIC of claim 1, wherein the photonic element consists essentially of silicon and is selected from the group consisting of:

a grating, a waveguide, and a multimode interference (MMI) coupler.

5. The PIC of claim 1, further comprising a group III-V semiconductor material bonded to the PPL, and wherein the ILD is disposed over the bonded group III-V semiconductor material.

6. A method of fabricating a photonic integrated circuit (PIC), the method comprising:

forming a photonic element comprising silicon on a substrate;

forming a silicon dioxide layer on the photonic element; and

forming a photonic passivation layer (PPL) by nitriding at least a portion of the silicon dioxide layer.

7. The method of claim 6, further comprising:

removing a portion of the silicon dioxide layer with a wet chemical etchant of silicon dioxide after forming the PPL.

8. The method of claim 6, wherein forming the silicon dioxide layer further comprises at least one of a thermal oxidation or radical oxidation of the photonic element, and wherein nitriding the silicon dioxide layer further comprises diffusing nitrogen through at least a portion of the silicon dioxide layer.

9. The method of claim 8, wherein the photonic element comprises a waveguide consisting essentially of silicon and wherein the method further comprises forming a hybrid laser by bonding a group III-V semiconductor material on the PPL disposed on the waveguide.

10. The method of claim 6, wherein the PPL is selectively formed over first surfaces of the photonic element while second surfaces remain free of the PPL.

11. A photonic integrated circuit (PIC), comprising:

a waveguide disposed on a silicon substrate; and

a hybrid semiconductor device including a crystalline group III-V semiconductor material bonded to the waveguide, wherein the group III-V semiconductor material has at least one sidewall surface offcut from the crystal cleavage planes of the group III-V semiconductor material.

12. The PIC of claim 11, wherein the crystalline group III-V semiconductor material has a (100) surface bonded to the waveguide, and wherein the sidewall surfaces are offcut from the {110} planes.

13. The PIC of claim 11, wherein the sidewall surface is offcut from the crystal cleavage planes by 5°

-10°

.

14. The PIC of claim 11, wherein the group III-V semiconductor material comprises an epitaxial stack including a plurality of group III-V semiconductor layers and wherein opposing sidewalls of the group III-V semiconductor material are all offcut by substantially the same amount to remain substantially parallel.

15. The PIC of claim 11, wherein the hybrid semiconductor device is a laser and wherein the waveguide comprises crystalline silicon.

16. A method of fabricating a hybrid semiconductor device, the method comprising:

singulating a crystalline group III-V semiconductor substrate into die by cutting the die edges misaligned from the crystal cleavage planes of the group III-V semiconductor material;

bonding a surface of a group III-V semiconductor material layer disposed on the group III-V semiconductor die to surface on a silicon semiconductor substrate; and

thinning the bonded group III-V semiconductor die by removing a bulk of the group III-V semiconductor substrate material from the group III-V semiconductor material layer.

17. The method of claim 16, wherein removing the group III-V semiconductor substrate further comprises a chemical wet etching process.

18. The method of claim 16, wherein the singulating comprises at least one of a laser singulation process or a saw dicing process.

19. The method of claim 18, wherein the laser-based dicing process further comprises offcutting the die edges with a laser micro jet.

20. The method of claim 16, wherein bonding the surface of the group III-V semiconductor material layer further comprises bonding a (100) surface of a epitaxial layer, and wherein the surface on the silicon substrate is a surface of a waveguide comprising at least one of silicon and silicon dioxide.

21. A semiconductor device, comprising:

a p-type group III-V semiconductor material layer disposed over a substrate;

an n-type group III-V semiconductor material layer disposed over the substrate; and

a contact metallization disposed over both the p-type and n-type group III-V semiconductor material layers, wherein the contact metallization comprises a NiGe alloy.

22. The device of claim 21, wherein contact metallization consists essentially of a the NiGe alloy disposed directly on the n-type group III-V semiconductor material layer, and the NiGe alloy disposed over the p-type group III-V semiconductor material layer with a diffusion barrier disposed there between.

23. The device of claim 21, wherein the substrate comprises silicon and wherein the p-type group III-V semiconductor material layer comprises Ga and As and wherein the n-type group III-V semiconductor material layer comprises In and P.

24. The device of claim 23, wherein the p-type group III-V semiconductor material layer consists essentially of InGaAs and wherein the n-type group III-V semiconductor material layer consists essentially of InP.

25. The device of claim 21, wherein the atomic ratio of Ni to Ge in the NiGe alloy is between 1.5:

1 and 5;

1.

26-31. -31. (canceled)