BACK PLANE OF FLAT PANEL DISPLAY AND METHOD OF MANUFACTURING THE SAME

• US 20140312315A1
• Filed: 08/27/2013
• Published: 10/23/2014
• Est. Priority Date: 04/18/2013
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Cho, Young-Mi, Kim, Kwang-Suk, Kang, Il-Joon, Kim, Tae-Young
• Application Number:
  US14/011,700
• Publication Number:
  US 20140312315A1
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass

Abstract

According to an aspect of the present invention, there is provided a back plane for a flat-panel display device and a method of manufacturing the same. The back plane including: a substrate; a gate electrode on the substrate; a first insulation layer on the substrate and covering the gate electrode; a semiconductor layer on the first insulation layer and corresponding to the gate electrode; and a source electrode and a drain electrode on the semiconductor layer and electrically coupled to respective portions of the semiconductor layer. Here, the semiconductor layer includes indium, tin, zinc, and gallium, and an atomic concentration of the gallium is from about 5% to about 15%.

Claims

1. A back plane for a flat-panel display device, the back plane comprising:

a substrate;

a gate electrode on the substrate;

a first insulation layer on the substrate and covering the gate electrode;

a semiconductor layer on the first insulation layer and corresponding to the gate electrode; and

a source electrode and a drain electrode on the semiconductor layer and electrically coupled to respective portions of the semiconductor layer,

wherein the semiconductor layer comprises indium, tin, zinc, and gallium, and

wherein an atomic concentration of the gallium is from about 5% to about 15%.

2. The back plane of claim 1, wherein the semiconductor layer is formed by using a target comprising an oxide of indium, tin, and zinc and gallium via sputtering.

3. The back plane of claim 1, further comprising a third insulation layer on the first insulation layer and covering the source electrode and the drain electrode,

wherein the third insulation layer has a third hole exposing a portion of the source electrode or the drain electrode.

4. The back plane of claim 3, further comprising:

a pixel electrode on the third insulation layer, in the third hole, and electrically coupled to the source electrode or the drain electrode;

an intermediate layer on the pixel electrode and comprising an organic emissive layer; and

a counter electrode facing the pixel electrode across the intermediate layer.

5. The back plane of claim 4, further comprising a fourth insulation layer on the third insulation layer, covering edges of the pixel electrode, and having an opening exposing at least a portion of the pixel electrode.

6. The back plane of claim 1, wherein the semiconductor layer comprises an oxide of indium, tin, and zinc.

7. The back plane of claim 1, further comprising a second insulation layer on the first insulation layer, covering the semiconductor layer, and having a first hole and a second hole exposing portions of the semiconductor layer,

wherein the source electrode and the drain electrode are on the second insulation layer and are in the first hole and the second hole, respectively.

8. A method of manufacturing a back plane for a flat-panel display device, the method comprising:

a first masking operation forming a gate electrode on a substrate;

forming a first insulation layer on the substrate to cover the gate electrode;

a second masking operation forming a semiconductor layer on the first insulation layer to correspond to the gate electrode;

a third masking operation forming a second insulation layer having a first hole and a second hole exposing respective portions of the semiconductor layer, the second insulation layer covering the semiconductor layer and being on the first insulation layer; and

a fourth masking operation forming a source electrode and a drain electrode on the semiconductor layer, the source electrode and the drain electrode being electrically coupled to the respective portions of the semiconductor layer,

wherein the semiconductor layer comprises indium, tin, zinc, and gallium, and

wherein an atomic concentration of the gallium is from about 5% to about 15%.

9. The method of claim 8, wherein the semiconductor layer is formed by using a target comprising an oxide of indium, tin, and zinc and gallium via sputtering.

10. The method of claim 8, further comprising a fifth masking operation forming a third insulation layer on the first insulation layer covering the source electrode and the drain electrode and having a third hole exposing a portion of the source electrode or the drain electrode.

11. The method of claim 10, further comprising a sixth masking operation forming a pixel electrode on the third insulation layer and in the third hole, the pixel electrode being electrically coupled to the source electrode or the drain electrode.

12. The method of claim 11, further comprising a seventh masking operation forming a fourth insulation layer on the third insulation layer covering edges of the pixel electrode and having an opening exposing at least a portion of the pixel electrode,

13. The method of claim 8, wherein the semiconductor layer comprises an oxide of indium, tin, and zinc.

14. The method of claim 8, wherein the source electrode and the drain electrode are formed on the second insulation layer and in the first hole and the second hole, respectively.

15. The method of claim 14, further comprising:

forming an intermediate layer on the pixel electrode, the intermediate layer comprising an organic emissive layer; and

forming a counter electrode facing the pixel electrode across the intermediate layer.

16. A display device comprising:

a substrate; and

a semiconductor layer on the substrate, the semiconductor layer comprising indium, tin, zinc, and gallium,

wherein an atomic concentration of the gallium is from about 5% to about 15%.

17. The display device of claim 16, wherein the semiconductor layer comprises an oxide of indium, tin, and zinc.

18. The display device of claim 17, further comprising a transistor on the substrate, the transistor comprising the semiconductor layer.