METHOD FOR BONDING SEMICONDUCTOR SUBSTRATES

• US 20140312359A1
• Filed: 07/02/2014
• Published: 10/23/2014
• Est. Priority Date: 11/29/2011
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Pham, Nga Phuong, Rosmeulen, Maarten, Vandevelde, Bart
• Granted Patent: US 9,105,827 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 33/005 Processes
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate.

Claims

1. A semiconductor device comprising a wafer portion, a device portion on one side of the wafer portion, and a stress compensation layer on the opposite side of the wafer portion.

2. The device of claim 1, further comprising a protection layer on the stress compensation layer.

3. The device of claim 1, further comprising a diffusion-inhibiting layer situated between the wafer portion and the stress compensation layer.

4. The device of claim 1, wherein the device is a GaNLED device.