POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20140312383A1
• Filed: 07/02/2014
• Published: 10/23/2014
• Est. Priority Date: 11/29/2012
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Park, Jae Hoon, Seo, Dong Soo, SONG, In Hyuk, Jang, Chang Su
• Granted Patent: US 9,245,986 B2
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A power semiconductor device may include: abase substrate including a first conductive type drift layer; a second conductive type semiconductor substrate disposed on the other surface of the base substrate; a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer; a second conductive type well layer disposed inside of one surface of the base substrate; a trench formed from one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction; a first insulation film disposed on a surface of the base substrate; and a first electrode disposed in the trench. A peak point of an impurity doping concentration of the diffusion layer in a transverse direction may be positioned in a region contacting a side surface of the trench.

Claims

1. A power semiconductor device comprising:

a base substrate having one surface and an other surface opposing the one surface and comprising a first conductive type drift layer;

a second conductive type semiconductor substrate disposed on the other surface of the base substrate;

a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer;

a second conductive type well layer disposed under the one surface of the base substrate;

a trench formed from the one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a first direction;

an insulation film disposed on the one surface of the base substrate including an inner wall of the trench; and

a first electrode disposed in the trench,

wherein a peak point of an impurity doping concentration of the diffusion layer in a second direction perpendicular to the first direction is positioned in a region contacting a side surface of the trench.

2. The power semiconductor device of claim 1, wherein the first direction is a depth direction, and the second direction is a transverse direction.

3. The power semiconductor device of claim 1, wherein a peak point of an impurity doping profile of the diffusion layer in the first direction is positioned in a region between a lower surface of the well layer and a lower surface of the trench.

4. The power semiconductor device of claim 1, wherein a peak point of an impurity doping profile of the well layer in the first direction is positioned in the one surface of the base substrate.

5. The power semiconductor device of claim 1, wherein the diffusion layer is formed in a semicircular shape on at least one side of a central portion of the trench and partially overlaps with another diffusion layer adjacent thereto.

6. The power semiconductor device of claim 1, wherein a peak point of an impurity doping profile of the diffusion layer in the first direction is formed to be spaced apart from the well layer in the first direction.

7. A power semiconductor device comprising:

a base substrate having one surface and an other surface opposing the one surface and comprising a first conductive type drift layer;

a second conductive type semiconductor substrate formed on the other surface of the base substrate;

a first conductive type diffusion layer formed in the base substrate and having an impurity concentration higher than that of the drift layer;

a second conductive type well layer formed under the one surface of the base substrate;

a trench formed from the one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction;

a first insulation film formed on the one surface of the base substrate including an inner wall of the trench; and

a first electrode formed in the trench,

wherein a peak point of an impurity doping profile of the diffusion layer in the depth direction is positioned in a region between a lower surface of the well layer and a lower surface of the trench.

8. A method of manufacturing a power semiconductor device, the method comprising:

preparing a base substrate having one surface and an other surface opposing the one surface and comprising a first conductive type drift layer;

forming an etching mask having an open part on the one surface of the base substrate;

forming a primary trench corresponding to the open part from the one surface of the base substrate in a depth direction;

forming a first conductive type diffusion layer having an impurity concentration higher than the drift layer by ion implanting a first conductive type impurity into the primary trench and performing thermal diffusion treatment so that the implanted impurity diffuses toward other primary trenches adjacent thereto;

completing a final trench by forming a secondary trench so as to be extended from a lower surface of the primary trench in the depth direction and penetrate through the diffusion layer; and

forming a second conductive type well layer in the one surface of the base substrate.

9. The method of claim 8, wherein a peak point of an impurity doping concentration of the diffusion layer in a transverse direction is positioned in a region contacting a side surface of the final trench.

10. The method of claim 8, wherein a peak point of an impurity doping profile of the diffusion layer in the depth direction is positioned in a region between a lower surface of the well layer and a lower surface of the final trench.

11. The method of claim 8, wherein the forming of the well layer is performed by implanting a second conductive type impurity into the one surface of the base substrate so that a peak point of a doping profile of the well layer is positioned in the one surface of the base substrate.