CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

• US 20140312478A1
• Filed: 04/17/2014
• Published: 10/23/2014
• Est. Priority Date: 04/19/2013
• Status: Active Grant

• Current Assignee: Xintec Incorporated
• Original Assignee: Xintec Incorporated
• Inventors: LIN, Chia-Sheng, HO, Yen-Shih, LIU, Tsang-Yu
• Granted Patent: US 9,406,590 B2
• Time in Patent Office: Days
• US Class Current: 257/667
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/494 Connecting portions
• CPC Class Codes: H01L 2224/8536 Bonding interfaces of the semiconductor or solid state body
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A chip package is provided. The chip package comprises a semiconductor chip, an isolation layer, a redistributing metal layer, and a bonding pad. The semiconductor chip has a first conducting pad disposed on a lower surface, and a first hole corresponding to the first conducting pad. The first hole and the isolation layer extend from an upper surface to the lower surface to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has a redistributing metal line corresponding to the first conducting pad, the redistributing metal line is connected to the first conducting pad through the opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the first conducting pad to the bonding pad. A method thereof is also provided.

Claims

1. A chip package, comprising:

a semiconductor chip with an upper surface and a lower surface, the semiconductor chip having at least one first conducting pad disposed on the lower surface, and a first hole corresponding to the first conducting pad on the lower surface, the first hole extending from the upper surface to the lower surface to expose the first conducting pad;

an isolation layer extending from the upper surface to the lower surface, part of the isolation layer positioned in the first hole, wherein the isolation layer has at least one opening to expose the first conducting pad;

a redistributing metal layer disposed on the isolation layer and having at least one redistributing metal line corresponding to the first conducting pad, and the redistributing metal line electrically connecting to the first conducting pad through the opening; and

at least one bonding pad disposed on the isolation layer and positioned at a side of the semiconductor chip,

wherein the redistributing metal line extends to the bonding pad to electrically connect the bonding pad positioned at the side and the first conducting pad disposed on the lower surface of the semiconductor chip.

2. The chip package of claim 1, wherein the first conducting pad is positioned at other side without being positioned at the side where the bonding pad is positioned.

3. The chip package of claim 2, further comprising:

at least one first bonding wire electrically connected to the bonding pad; and

a printed circuit board, wherein the first bonding wire extends from the bonding pad to the printed circuit board and is electrically connected to the printed circuit board.

4. The chip package of claim 2, further comprising:

at least one third bonding wire electrically connected to the first conducting pad;

a microelectromechanical system (MEMS) disposed below the lower surface; and

a printed circuit board, wherein the third bonding wire extends from the first conducting pad, and is electrically connected to the printed circuit board.

5. The chip package of claim 2, further comprising:

at least one third bonding wire electrically connected to the first conducting pad;

at least one solder ball electrically connected to the bonding pad;

a chip electrically connected to the bonding pad through the solder ball; and

a printed circuit board, wherein the third bonding wire extends from the first conducting pad, and is electrically connected to the printed circuit board.

6. The chip package of claim 1, wherein the semiconductor chip further comprises:

at least one second conducting pad disposed on the lower surface and positioned at the side of the semiconductor chip; and

at least one second hole corresponding to the second conducting pad, the second hole extending from the upper surface to the lower surface to expose the second conducting pad, and the isolation layer having at least one opening to expose the second conducting pad,

wherein an angel between a sidewall of the second hole and the lower surface is substantially 55-65 degree.

7. The chip package of claim 6, further comprising:

at least one first bonding wire electrically connected to the bonding pad;

at least one second bonding wire electrically connected to the second conducting pad; and

a printed circuit board, wherein the first bonding wire and the second bonding wire respectively extends from the bonding pad and the second conducting pad to the printed circuit board, and the first bonding wire, the second bonding wire are electrically connected to the printed circuit board.

8. The chip package of claim 7, wherein the second bonding wire has a connection to the second conducting pad, and a distance between the connection and sidewalls of the second hole is substantially greater than 50 μ

m.

9. The chip package of claim 1, further comprising:

at least one dam structure disposed on the lower surface of the semiconductor chip; and

a protective lid, wherein the dam structure is sandwiched by the protective lid and the semiconductor chip.

10. A method of manufacturing a chip package, comprising:

forming a semiconductor chip with an upper surface and a lower surface, the semiconductor chip having at least one first conducting pad disposed on the lower surface, and at least one first hole extending from the upper surface to the lower surface to expose the first conducting pad;

forming an isolation layer extending from the upper surface to the lower surface, part of the isolation layer is disposed in the first hole, wherein the isolation layer has at least one opening to expose the first conducting pad;

forming at least one redistributing metal line on the isolation layer, the redistributing metal line electrically connected to the first conducting pad through the opening; and

forming at least one bonding pad disposed on the isolation layer and positioned at a side of the semiconductor chip,

wherein the redistributing metal line extends to the bonding pad to electrically connect the bonding pad positioned at the side and the first conducting pad disposed on the lower surface of the semiconductor chip.

11. The method of claim 10, wherein the first conducting pad is formed at other sides of the semiconductor chip without being formed at the side where the bonding pad is formed.

12. The method of claim 11, further comprising:

bonding at least one first bonding wire electrically connected to the bonding pad; and

providing a printed circuit board, wherein the first bonding wire extends from the bonding pad to the printed circuit board such that the bonding pad is electrically connected to the printed circuit board.

13. The method of claim 10, wherein the operation of forming the semiconductor chip further comprises:

forming at least one second conducting pad disposed on the lower surface and positioned at the side of the semiconductor chip; and

forming at least one second hole extending from the upper surface to the lower surface to expose the second conducting pad, and the isolation layer having at least one opening to expose the second conducting pad,

wherein, an angle between a sidewall of the second hole and the lower surface is substantially 55-65 degree.

14. The method of claim 13, further comprising:

bonding at least one first bonding wire electrically connected to the bonding pad;

bonding at least one second bonding wire electrically connected to the second conducting pad; and

providing a printed circuit board, wherein the first bonding wire and the second bonding wire respectively extends from the bonding pad and the second conducting pad to the printed circuit board, and the bonding pad and the second conducting pad are respectively electrically connected to the printed circuit board.

15. The method of claim 14, wherein the second bonding wire has a connection to the second conducting pad, and a distance between the connection and sidewalls of the second hole is substantially greater than 50 μ

m.

16. The method of claim 10, further comprising:

forming at least one dam structure disposed on the lower surface of the semiconductor chip; and

providing a protective lid, wherein the dam structure is sandwiched by the protective lid and the semiconductor chip.