HIGH-VOLTAGE MULTI-LEVEL SHIFTER FOR ULTRASOUND APPLICATIONS AND TRANSMIT/RECEIVE CHANNEL FOR ULTRASOUND APPLICATIONS USING SAID LEVEL SHIFTER

• US 20140312954A1
• Filed: 04/18/2014
• Published: 10/23/2014
• Est. Priority Date: 04/23/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Ghisu, Davide Ugo, Rossi, Sandro, Ricciardo, Antonio
• Granted Patent: US 8,947,150 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 5/12 by steepening leading or trailing edges

Abstract

A multi-level shifter includes a first branch having first and second transistors coupled between a higher voltage terminal and a lower voltage terminal. The multi-level shifter comprises a second branch, in parallel with the first branch, having: a third transistor, coupled between said higher voltage reference terminal and an output node, a fourth switching transistor coupled between said output node and said lower voltage terminal. Said third and fourth transistors have respective control terminals controlled by drain terminals of said first and second transistors, respectively. The shifter includes a bidirectional battery coupled between said drain terminals of said first and second transistors to supply first and second voltages having the same magnitude and different polarities. Said fourth transistor is controlled according to the first voltage when said first transistor is turned on and said third transistor is controlled according to the second voltage when said second transistor is turned on.

Claims

1. A high-voltage multi-level shifter for ultrasound applications, comprising:

a first branch having a high-voltage PMOS first transistor and a high-voltage NMOS second transistor electrically coupled with each other between a first higher voltage reference terminal and a first lower voltage reference terminal, said first and second transistors having respective drain terminals coupled together and respective control terminals;

a second branch, electrically coupled in parallel to the first branch, having;

a high-voltage NMOS third transistor electrically coupled between said first higher voltage reference terminal and an output node, and

a high-voltage PMOS fourth transistor electrically coupled between said output node and said first lower voltage reference terminal,

said third and fourth transistors having respective control terminals configured to be controlled by said drain terminals of said first transistor and said second transistor respectively, and

said first and fourth transistors having the same current-carrying capacity, and said second and third transistors being configured as having the same current-carrying capacity; and

a bidirectional battery coupled between said drain terminals of said first transistor and said second transistor and configured to supply first and second voltage values having the same magnitude and different polarities;

said bidirectional battery being configured to control said fourth transistor according to the first voltage value when said first transistor is turned on; and

said bidirectional battery being configured to control said third transistor being controlled according to the second voltage value when said second transistor is turned on.

2. The high-voltage multi-level shifter as claimed in claim 1, comprising:

a first low-voltage diode having a cathode terminal coupled to said drain terminal of said first transistor and an anode terminal coupled to said output node; and

a second low-voltage diode having a cathode terminal coupled to said output node and an anode terminal coupled to said drain terminal of said second switching transistor,

wherein said first voltage value is equal to said control voltage less a voltage across said first diode and the second voltage value is equal to the control voltage less a voltage across said second diode.

3. The high-voltage multi-level shifter as claimed in claim 1, wherein said bidirectional battery comprises a plurality of low-voltage diodes in an antiparallel arrangement.

4. The high-voltage multi-level shifter as claimed in claim 1, wherein said first, second, third and fourth transistors are MOS transistors configured as having the same current-carrying capacity.

5. The high-voltage multi-level shifter as claimed in claim 1, comprising:

a fifth transistor and a third diode coupled in series with each other between a voltage reference terminal and said drain terminal of said first transistor;

a sixth transistor and a fourth diode coupled in series with each other between said voltage reference terminal and said drain terminal of said second transistor; and

third and fourth input drivers configured to respectively control respective control terminals of said fifth and sixth transistors;

said fifth transistor being a high-voltage P-channel MOS transistor, and said sixth transistor being a high-voltage N-channel MOS transistor;

said fifth and sixth transistors being configured as having a current-carrying capacity lower than a current-carrying capacity of said first, second, third and fourth transistors.

6. The high voltage multi-level shifter as claimed in claim 5, wherein the current-carrying capacity of said fifth and sixth transistors is half the current-carrying capacity of said first, second, third and fourth transistors.

7. The high-voltage multi-level shifter as claimed in claim 5, wherein:

a cathode terminal of said third diode is coupled with said drain terminal of said first switching transistor;

an anode terminal of said fourth diode is coupled with said drain terminal of said second switching transistor.

8. The high-voltage multi-level shifter as claimed in claim 5, comprising:

a fifth diode coupled with said first switching transistor, in which a cathode terminal of said fifth diode is connected with said control terminal of said third switching transistor;

a sixth diode coupled with said second switching transistor, in which an anode terminal of said sixth diode is connected with said control terminal of said fourth switching transistor;

a third branch coupled to the first and second branches, and having;

a seventh transistor and a seventh diode, coupled in series with each other between a second higher reference voltage terminal and said control terminal of said third transistor, in which a cathode terminal of the seventh diode is coupled with said control terminal of said third transistor;

an eighth transistor and an eighth diode, coupled with each other between a second lower reference voltage terminal and said control terminal of said fourth switching transistor, in which an anode terminal of said eighth diode is coupled with said control terminal of said fourth transistor;

said seventh and eighth transistors having respective gates coupled to and controlled by fifth and sixth input drivers;

said seventh transistor being a high-voltage P-channel MOS transistor, and said eighth transistor being a high-voltage N-channel MOS transistor.

9. The high-voltage multi-level shifter as claimed in claim 8, wherein said second branch comprises:

a ninth transistor coupled between said first higher voltage reference terminal and said drain terminal of said third transistor, said ninth transistor having a gate terminal connected with said gate terminal of said first transistor;

a tenth transistor coupled in series between said first lower voltage reference terminal and said drain terminal of said fourth transistor, said tenth transistor having a gate terminal connected with said gate terminal of said second transistor.

10. The high-voltage multi-level shifter as claimed in claim 9, wherein:

said ninth transistor is a high-voltage P-channel MOS transistor having a current-carrying capacity that is lower than at least one of said first and third transistors;

said tenth transistor is a high-voltage N-channel MOS transistor having a current-carrying capacity that is lower than at least one of said second and fourth transistors.

11. The high-voltage multi-level shifter as claimed in claim 9, comprising:

a ninth diode having a cathode terminal coupled with a drain terminal of said ninth transistor and an anode terminal coupled with a source terminal of said seventh transistor,

a tenth diode having a cathode terminal coupled with a drain terminal of said eighth transistor and an anode terminal coupled with a drain terminal of said fourth transistor.

12. A transmit/receive channel for ultrasound applications comprising:

a connection terminal configured to be coupled to a piezoelectric transducer;

a low-voltage output terminal;

an anti-noise block;

a receive switch coupled between said connection terminal and a low-voltage output terminal and configured to pass a receive signal from the connection terminal to the low-voltage output terminal; and

a high-voltage multi-level shifter that includes;

an output terminal, the anti-noise block being coupled between the output terminal of the high-voltage multi-level shifter and the connection terminal;

a first branch having a high-voltage PMOS first transistor and a high-voltage NMOS second transistor electrically coupled with each other between a first higher voltage reference terminal and a first lower voltage reference terminal, said first and second transistors having respective drain terminals coupled together and respective control terminals;

first and second input drivers configured to control the control terminals of the first and second transistors,

a second branch, electrically coupled in parallel to the first branch, having;

a high-voltage NMOS third transistor electrically coupled between said first higher voltage reference terminal and an output node, and

a high-voltage PMOS fourth transistor electrically coupled between said output node and said first lower voltage reference terminal,

said third and fourth transistors having respective control terminals configured to be controlled by said drain terminals of said first transistor and said second transistor respectively, and

said first and fourth transistors having the same current-carrying capacity, and said second and third transistors being configured as having the same current-carrying capacity; and

a bidirectional battery coupled between said drain terminals of said first transistor and said second transistor and configured to supply first and second voltage values having the same magnitude and different polarities;

said bidirectional battery being configured to control said fourth transistor according to the first voltage value when said first transistor is turned on; and

said bidirectional battery being configured to control said third transistor being controlled according to the second voltage value when said second transistor is turned on.

13. The transmit/receive channel as claimed in claim 12, the high-voltage multi-level shifter including:

a first low-voltage diode having a cathode terminal coupled to said drain terminal of said first transistor and an anode terminal coupled to said output node; and

a second low-voltage diode having a cathode terminal coupled to said output node and an anode terminal coupled to said drain terminal of said second switching transistor,

wherein said first voltage value is equal to said control voltage less a voltage across said first diode and the second voltage value is equal to the control voltage less a voltage across said second diode.

14. The transmit/receive channel as claimed in claim 12, wherein said bidirectional battery comprises a plurality of low-voltage diodes in an antiparallel arrangement.

15. The transmit/receive channel as claimed in claim 12, the high-voltage multi-level shifter including:

a fifth transistor and a third diode coupled in series with each other between a voltage reference terminal and said drain terminal of said first transistor;

a sixth transistor and a fourth diode coupled in series with each other between said voltage reference terminal and said drain terminal of said second transistor; and

third and fourth input drivers configured to respectively control respective control terminals of said fifth and sixth transistors;

said fifth transistor being a high-voltage P-channel MOS transistor, and said sixth transistor being a high-voltage N-channel MOS transistor;

said fifth and sixth transistors being configured as having a current-carrying capacity lower than a current-carrying capacity of said first, second, third and fourth transistors.

16. The transmit/receive channel as claimed in claim 15, wherein:

a cathode terminal of said third diode is coupled with said drain terminal of said first switching transistor; and

an anode terminal of said fourth diode is coupled with said drain terminal of said second switching transistor.

17. The transmit/receive channel as claimed in claim 15, the high-voltage multi-level shifter including:

a fifth diode coupled with said first switching transistor, in which a cathode terminal of said fifth diode is connected with said control terminal of said third switching transistor;

a sixth diode coupled with said second switching transistor, in which an anode terminal of said sixth diode is connected with said control terminal of said fourth switching transistor;

a third branch coupled to the first and second branches, and having;

a seventh transistor and a seventh diode, coupled in series with each other between a second higher reference voltage terminal and said control terminal of said third transistor, in which a cathode terminal of the seventh diode is coupled with said control terminal of said third transistor;

an eighth transistor and an eighth diode, coupled with each other between a second lower reference voltage terminal and said control terminal of said fourth switching transistor, in which an anode terminal of said eighth diode is coupled with said control terminal of said fourth transistor;

said seventh and eighth transistors having respective gates coupled to and controlled by fifth and sixth input drivers;

said seventh transistor being a high-voltage P-channel MOS transistor, and said eighth transistor being a high-voltage N-channel MOS transistor.

18. The transmit/receive channel as claimed in claim 17, wherein said second branch comprises:

a ninth transistor coupled between said first higher voltage reference terminal and said drain terminal of said third transistor, said ninth transistor having a gate terminal connected with said gate terminal of said first transistor;

a tenth transistor coupled in series between said first lower voltage reference terminal and said drain terminal of said fourth transistor, said tenth transistor having a gate terminal connected with said gate terminal of said second transistor.

19. The transmit/receive channel as claimed in claim 18, the high-voltage multi-level shifter including:

a ninth diode having a cathode terminal coupled with a drain terminal of said ninth transistor and an anode terminal coupled with a source terminal of said seventh transistor,

a tenth diode having a cathode terminal coupled with a drain terminal of said eighth transistor and an anode terminal coupled with a drain terminal of said fourth transistor.

20. A multi-level shifter, comprising:

a first branch having a first transistor and a second transistor electrically coupled with each other between a first higher voltage reference terminal and a first lower voltage reference terminal, said first and second transistors having respective control terminals;

a second branch, electrically coupled in parallel to the first branch, and including;

a third transistor electrically coupled between said first higher voltage reference terminal and an output node, and

a fourth transistor electrically coupled between said output node and said first lower voltage reference terminal; and

a bidirectional battery coupled between said first transistor and said second transistor and configured to supply first and second voltage values having the same magnitude and different polarities, said bidirectional battery being configured to control said fourth transistor according to the first voltage value when said first transistor is turned on, and said bidirectional battery being configured to control said third transistor according to the second voltage value when said second transistor is turned on.

21. The multi-level shifter as claimed in claim 20, comprising:

a first diode having a cathode terminal coupled to said drain terminal of said first transistor and an anode terminal coupled to said output node; and

a second diode having a cathode terminal coupled to said output node and an anode terminal coupled to said drain terminal of said second switching transistor,

22. The multi-level shifter as claimed in claim 20, wherein said bidirectional battery comprises a plurality of low-voltage diodes in an antiparallel arrangement.

23. The multi-level shifter as claimed in claim 20, comprising:

a fifth transistor and a third diode coupled in series with each other between a voltage reference terminal and said drain terminal of said first transistor;

a sixth transistor and a fourth diode coupled in series with each other between said voltage reference terminal and said drain terminal of said second transistor; and

third and fourth input drivers configured to respectively control respective control terminals of said fifth and sixth transistors;

said fifth and sixth transistors being configured as having a current-carrying capacity lower than a current-carrying capacity of said first, second, third and fourth transistors.