Color Buffer Compression

• US 20140313211A1
• Filed: 04/22/2013
• Published: 10/23/2014
• Est. Priority Date: 04/22/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Akenine-Moller, Tomas G., Nilsson, Jim K., Hasselgren, Jon N., Andersson, Magnus
• Granted Patent: US 9,582,847 B2
• Time in Patent Office: Days
• US Class Current: 345/531
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 11/001 Texturing; Colouring; Generation of texture or colour inpainting G06T5/77
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture

Abstract

In accordance with some embodiments, a mask or table may be maintained to record information about whether or not each pixel within a tile is cleared. As used herein, a “cleared” tile is one that is not covered by any other depicted objects. The clear mask may store a bit per pixel or sample to indicate whether the pixel or sample contains a color value or whether it is cleared. As a result, the compression ratio may be increased for partially covered tiles in some embodiments.

Claims

1. A computer executed method comprising:

determining whether a tile of pixels or samples has a constant or varying alpha value;

determining a number of cleared pixels or samples for the tile; and

based on the alpha value determination and the number of cleared pixels or samples, determining how to store the tile.

2. The method of claim 1 including using two bits to store the alpha value determination.

3. The method of claim 1 including providing three alpha value determinations including constant zero, constant one and varying.

4. The method of claim 1 including storing a clear bit for each pixel or sample of the tile to indicate whether the pixel or sample is cleared.

5. The method of claim 4 including determining a maximum number of clear bits for a tile to be storable in compressed form.

6. The method of claim 5 including determining a maximum number of clear bits for each of constant and varying alpha values to compress a tile for storage in compressed form.

7. One or more non-transitory computer readable media storing instructions that cause a processor to perform a sequence comprising:

determining whether a tile of pixels or samples has a constant or varying alpha value;

determining a number of cleared pixels or samples for the tile; and

based on the alpha value determination and the number of cleared pixels or samples, determining how to store the tile.

8. The media of claim 7, said sequence including using two bits to store the alpha value determination.

9. The media of claim 7, said sequence including providing three alpha value determinations including constant zero, constant one and varying.

10. The media of claim 7, said sequence including storing a clear bit for each pixel or sample of the tile to indicate whether the pixel or sample is cleared.

11. The media of claim 10, said sequence including determining a maximum number of clear bits for a tile to be storable in compressed form.

12. The media of claim 11, said sequence including determining a maximum number of clear bits for each of constant and varying alpha values to compress a tile for storage in compressed form.

13. An apparatus comprising:

a processor to perform a sequence, wherein to perform the sequence, the processor is to;

determine whether a tile of pixels or samples has a constant or varying alpha value, determine a number of cleared pixels or samples for the tile, and based on the alpha value determination and the number of cleared pixels or samples, determine how to store the tile; and

a storage coupled to said processor.

14. The apparatus of claim 13, wherein to perform said sequence, the processor is to use two bits to store the alpha value determination.

15. The apparatus of claim 13, wherein to perform said sequence, the processor is to provide three alpha value determinations including constant zero, constant oneand varying.

16. The apparatus of claim 13, wherein to perform said sequence, the processor is to store a clear bit for each pixel or sample of the tile to indicate whether the pixel or sample is cleared.

17. The apparatus of claim 16, wherein to perform said sequence, the processor is to determine a maximum number of clear bits for a tile to be storable in compressed form.

18. The apparatus of claim 17, wherein to perform said sequence, the processor is to determine a maximum number of clear bits for each of constant and vary alpha values to compress a tile for storage in compressed form.

19. The apparatus of claim 13 including an operating system.

20. The apparatus of claim 13 including a battery.

21. The apparatus of claim 13 including firmware and a module to update said firmware.

22. An apparatus comprising:

a memory; and

a processor coupled to said memory to determine whether a pixel is cleared because it is not covered by any other depicted object and only storing color values in said memory for pixels that are not cleared.

23. The apparatus of claim 22 wherein said processor is a graphics processing unit.

24. The apparatus of claim 22 including said processor to store a clear mask of 1 bit per pixel in each compressed tile.

25. The apparatus of claim 24 said processor to use two mask bits to indicate whether the alpha value is zero, one or not constant over the whole tile.

26. The apparatus of claim 25 said processor to store color values in full precision.

27. The apparatus of claim 22 said processor to use a bit of delta value to denote a cleared pixel.

28. The apparatus of claim 22 including an operating system.

29. The apparatus of claim 22 including a battery.

30. The apparatus of claim 22 including firmware and a module to update said firmware.