CONTACT STRUCTURE EMPLOYING A SELF-ALIGNED GATE CAP

• US 20140315379A1
• Filed: 09/16/2013
• Published: 10/23/2014
• Est. Priority Date: 04/18/2013
• Status: Active Grant

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: He, Hong, Tseng, Chiahsun, Yin, Yunpeng, Yeh, Chun-chen
• Granted Patent: US 8,969,189 B2
• Time in Patent Office: Days
• US Class Current: 438/595
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion.

Claims

1. A method of forming a semiconductor structure comprising:

forming a gate structure including a stack of a gate dielectric and a gate electrode and over a portion of a semiconductor material layer;

forming a first dielectric material layer comprising a first dielectric material over said semiconductor material layer and said gate structure;

forming a second dielectric material layer comprising a second dielectric material that is different from said first dielectric material over said first dielectric material layer;

planarizing said second dielectric material layer to provide a planar top surface, wherein a top surface of said first dielectric material layer is physically exposed over said gate structure;

removing a portion of said first dielectric material layer from above said gate structure by an anisotropic etch employing said second dielectric material layer as an etch mask, wherein a cavity is formed over said gate structure;

forming a gate cap dielectric material portion by filling said cavity with at least a third dielectric material that is different from said first and second dielectric materials, said third dielectric material contacting sidewalls of said first dielectric material layer; and

forming a contact via hole through said second and first dielectric material layers employing another anisotropic etch that is selective to said third dielectric material.

3. The method of claim 1, wherein said another anisotropic etch comprises:

a first anisotropic etch step that etches said second dielectric material selective to said third dielectric material; and

a second anisotropic etch step that etches said first dielectric material selective to said third dielectric material.

4. The method of claim 3, further comprising forming a contact via structure by:

depositing a conductive material within said contact via hole and over said second dielectric material layer; and

removing portions of said conductive material from above a topmost surface of said second dielectric material layer.

5. The method of claim 1, further, comprising recessing a peripheral portion of said gate cap dielectric material portion during said forming of said contact via hole, wherein said contact via hole extends to a volume overlying said recessed peripheral portion of said gate cap dielectric material portion.

6. The method of claim 1, wherein outer sidewalls of said cavity are laterally offset outward from outer sidewalls of said gate structure by a same offset distance throughout an entire periphery of said gate structure.

7. The method of claim 1, wherein said third dielectric material comprises a dielectric metal oxide.

8. The method of claim 1, wherein said gate cap dielectric material portion is formed by:

depositing a third dielectric material layer in said cavity and over said second dielectric material layer;

depositing a fourth dielectric material layer over said third dielectric material layer;

removing portions of said fourth dielectric material layer outside an area of said cavity by planarization;

forming a fourth dielectric material portion in said cavity by recessing a remaining portion of said fourth dielectric material layer after said planarization;

depositing a fifth dielectric material layer on said fourth dielectric material portion; and

removing portions of said fifth dielectric material layer and said third dielectric material layer from above a top surface of said second dielectric material layer, wherein said gate cap dielectric portion comprises remaining portions of said third and fifth dielectric material layers and said fourth dielectric material portion.

9. The method of claim 1, further comprising forming a dielectric liner over said semiconductor material layer and said gate structure prior to forming said first dielectric material layer.

10. The method of claim 9, further comprising forming a gate spacer comprising a dielectric material around said gate structure prior to forming said dielectric liner.

2. (canceled)

11. A method of forming a semiconductor structure comprising:

forming a gate structure including a stack of a gate dielectric and a gate electrode and over a portion of a semiconductor material layer;

forming a first dielectric material layer comprising a first dielectric material over said semiconductor material layer and said gate structure;

forming a second dielectric material layer comprising a second dielectric material that is different from said first dielectric material over said first dielectric material layer;

planarizing said second dielectric material layer to provide a planar top surface, wherein a top surface of said first dielectric material layer is physically exposed over said gate structure;

removing a portion of said first dielectric material layer from above said gate structure by an anisotropic etch employing said second dielectric material layer as an etch mask, wherein a cavity is formed over said gate structure; and

forming a gate cap dielectric material portion by filling said cavity with at least a third dielectric material that is different from said first and second dielectric materials, said third dielectric material contacting sidewalls of said first dielectric material layer,

wherein said gate cap dielectric material portion is formed by;

depositing a third dielectric material layer in said cavity and over said second dielectric material layer;

depositing a fourth dielectric material layer over said third dielectric material layer;

removing portions of said fourth dielectric material layer outside an area of said cavity by planarization;

forming a fourth dielectric material portion in said cavity by recessing a remaining portion of said fourth dielectric material layer after said planarization;

depositing a fifth dielectric material layer on said fourth dielectric material portion; and

removing portions of said fifth dielectric material layer and said third dielectric material layer from above a top surface of said second dielectric material layer, wherein said gate cap dielectric portion comprises remaining portions of said third and fifth dielectric material layers and said fourth dielectric material portion.

12. The method of claim 11, further comprising forming a contact via hole through said second and first dielectric material layers employing another anisotropic etch that is selective to said third dielectric material.

13. The method of claim 12, wherein said another anisotropic etch comprises:

a first anisotropic etch step that etches said second dielectric material selective to said third dielectric material; and

a second anisotropic etch step that etches said first dielectric material selective to said third dielectric material.

14. The method of claim 13, further comprising forming a contact via structure by:

depositing a conductive material within said contact via hole and over said second dielectric material layer; and

removing portions of said conductive material from above a topmost surface of said second dielectric material layer.

15. The method of claim 12, further comprising recessing a peripheral portion of said gate cap dielectric material portion during said forming of said contact via hole, wherein said contact via hole extends to a volume overlying said recessed peripheral portion of said gate cap dielectric material portion.

16. The method of claim 11, wherein outer sidewalls of said cavity are laterally offset outward from outer sidewalls of said gate structure by a same offset distance throughout an entire periphery of said gate structure.

17. The method of claim 11, wherein said third dielectric material comprises a dielectric metal oxide.

18. The method of claim 11, further comprising forming a dielectric liner over said semiconductor material layer and said gate structure prior to forming said first dielectric material layer.

19. The method of claim 18, further comprising forming a gate spacer comprising a dielectric material around said gate structure prior to forming said dielectric liner.