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Scheduling in a Multicore Architecture

  • US 20140317378A1
  • Filed: 05/01/2014
  • Published: 10/23/2014
  • Est. Priority Date: 09/30/2005
  • Status: Active Grant
First Claim
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1. A method of scheduling executable transactions in a multicore processor comprising a plurality of processor elements, wherein at least one processor element comprises reconfigurable logic, the method comprising:

  • providing a configuration queue of executable transactions for a first configuration of the reconfigurable logic comprising one of a field programmable gate array (FPGA) or a memory, the executable transactions allocated to and ready for execution by the reconfigurable logic;

    outputting the executable transactions of the configuration queue to the reconfigurable processor element for execution when the reconfigurable logic is configured according to the first configuration; and

    reconfiguring the reconfigurable logic according to a second configuration when a pre-determined threshold is reached.

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