SUPPORT DEVICE, DESIGN SUPPORT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM

• US 20140317586A1
• Filed: 04/15/2014
• Published: 10/23/2014
• Est. Priority Date: 04/19/2013
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Amano, Yasuo, Arayama, Masashi, Makino, Sumiko
• Application Number:
  US14/253,248
• Publication Number:
  US 20140317586A1
• Time in Patent Office: Days
• US Class Current: 716/122
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A design support device includes placement determination unit, logic extraction unit, and logic placement unit. The placement determination unit performs the process of determining the optimum position of a first terminal of a first cell as a first position in which the inter-terminal wiring between the first cell and a second cell connected to the first cell through the first terminal is short. Furthermore, the logic placement unit performs the process of extracting one or more logical blocks including a logical block having the first terminal from the first cell, and arranging one or more logical blocks so that the first terminal may become close to the first position.

Claims

1. A design support device, comprising

a processor which performs processes of:

determining an optimum position of a first terminal of a first cell as a first position in which an inter-terminal wiring between the first cell and a second cell connected to the first cell through the first terminal is short;

extracting one or more logical blocks including a logical block having the first terminal from the first cell; and

placing one or more logical blocks so that the first terminal may become close to the first position.

2. The device according to claim 1, wherein the processes performed by the processor further comprises:

retrieving two or more mutually connected logical blocks from among two or more logical blocks when a logic extraction unit extracts the two or more logical blocks from the first cell;

setting respective placement orders of the two or more connected logical blocks so that each output destination of each connected logical block on an output side may be in a same direction in the two or more connected logical blocks; and

defining a placement of the two or more connected logical blocks as the set placement order when the two or more logical blocks are placed, and placing the two or more logical blocks so that the first terminal may become close to the first position.

3. The device according to claim 1, wherein the processes performed by the processor further comprises

extracting an area in which diffusion layers of the first cell are continuously placed as the one or more logical blocks.

4. The device according to claim 1, wherein the processes performed by the processor further comprises

determining the first position by averaging an influence of input signal timing against connected plurality cells when there are plurality cells which are connected to the first terminal.

5. The device according to claim 1, wherein the processes performed by the processor further comprises

obtaining a distance between the first terminal and the first position each time a placement of the one or more logical blocks is changed, and placing the one or more logical blocks for the placement with the shortest distance.

6. The device according to claim 1, wherein:

the first cell further comprises a second terminal connected to a third cell; and

the processes performed by the processor further comprises;

determining the optimum position of the second terminal as a second position in which a wiring length between the first cell and the third cell is short; and

placing the one or more logical blocks so that the second terminal may become close to the second position.

7. The device according to claim 6, wherein the processes performed by the processor further comprises

obtaining a total distance which is calculated to add a distance between the first terminal and the first position to a distance between the second terminal and the second position, and placing the one or more logical blocks so that the total distance may become minimized.

8. The device according to claim 1, further comprising

a storage unit which stores a placement of one or more logical blocks of the first cell, the placement being performed in a process of placing the logical blocks, wherein

the processes performed by the processor further comprises

when there is a third cell which is identical with the first cell in type and in which an optimum position of a terminal connected to another cell is set in a position corresponding to the first position, making a placement of one or more logical blocks of the third cell be identical with a placement of one or more logical blocks of the first cell.

9. The device according to claim 1, wherein

the processes performed by the processor further comprises

changing placement position of the one or more logical blocks and left-to-right reverse array of the one or more logical blocks, and placing the one or logical blocks so that the first terminal may become close to the first position.

10. An information processing method performed by a computer, the method comprising:

determining an optimum position of a first terminal of a first cell as a first position in which an inter-terminal wiring between the first cell and a second cell connected to the first cell through the first terminal is short;

extracting one or more logical blocks including a logical block having the first terminal from the first cell; and

placing one or more logical blocks so that the first terminal may become close to the first position.

11. The method according to claim 10 further comprises:

retrieving two or more mutually connected logical blocks from among the two or more logical blocks when two or more logical blocks are extracted from the first cell in the process of extracting one or more logical blocks from the first cell;

setting placement order of the two or more connected logical blocks so that an output destination of each connected logical block on an output signal side may be in an identical direction in the two or more connected and retrieved logical blocks; and

defining a placement of the two or more connected logical blocks as the set placement order in the process of setting a placement order when the two or more logical blocks are placing, and placing the two or more logical blocks so that the first terminal may become close to the first position.

12. A computer-readable recording medium which stores a program used by a computer to perform a process of designing a circuit, the process comprising:

determining an optimum position of a first terminal of a first cell as a first position in which an inter-terminal wiring between the first cell and a second cell connected to the first cell through the first terminal is short;

extracting one or more logical blocks including a logical block having the first terminal from the first cell; and

placing one or more logical blocks so that the first terminal may become close to the first position.

13. The recording medium according to claim 12, wherein the process further comprises:

retrieving two or more mutually connected logical blocks from among the two or more logical blocks when two or more logical blocks are extracted from the first cell in the process of extracting one or more logical blocks from the first cell;

setting placement order of the two or more connected logical blocks so that an output destination of each connected logical block on an output signal side may be in an identical direction in the two or more connected and retrieved logical blocks; and

defining a placement of the two or more connected logical blocks as the set placement order in the process of setting a placement order when the two or more logical blocks are placed, and placing the two or more logical blocks so that the first terminal may become close to the first position.