SEMICONDUCTOR DEVICE

• US 20140320180A1
• Filed: 07/10/2014
• Published: 10/30/2014
• Est. Priority Date: 04/02/2012
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: AKAHANE, Masashi
• Granted Patent: US 9,312,845 B2
• Time in Patent Office: Days
• US Class Current: 327/143
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/22 Modifications for ensuring a predetermined initial state when the supply voltage has been applied bi-stable generators H03K3/12
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 2217/0063 High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H03K 9/08 of duration- or width-mudulated pulses or of duty-cycle modulated pulses

Abstract

In aspects of the invention, a semiconductor device can include one level shift circuit that outputs a low-side input signal as a high-side signal upon raising a signal level, a pulse modulation circuit that operates in a low-side region, generates a data symbol constituted by or more bits and representing a set signal or a reset signal, where bit is defined as a combination of codes forming a pair. The pulse generation circuit can output the generated data symbol as an input signal of the level shift circuit. Also included can be a pulse demodulation circuit that operates in a high-side region, demodulates the data symbol outputted from the level shift circuit and generates a level-shifted set signal or reset signal; and a control circuit that controls conduction/non-conduction of the high-potential-side switching element on the basis of the level-shifted set signal or reset signal outputted from the pulse demodulation circuit.

Claims

1. A semiconductor device that performs, from among a high-potential-side switching element and a low-potential-side switching element, which are connected in series and which are interposed between a high-potential main power supply potential and a low-potential main power supply potential, drive control of the high-potential-side switching element,

the semiconductor device comprising:

one level shift circuit that outputs an input signal of a low-side region operating in a low-voltage potential system, as a signal of a high-side region operating in a nigh-voltage potential system, upon raising a signal level;

a pulse modulation circuit that operates in a low-side region, generates a data symbol constituted by 2 or more bits and representing a set signal or a reset signal, where 1 bit is defined as a combination of H, L codes forming a pair, and outputs the generated data symbol as an input signal of the level shift circuit;

a pulse demodulation circuit that operates in a high-side region, demodulates the data symbol outputted from the level shift circuit, and generates a level-shifted set signal or reset signal; and

a control circuit that controls conduction/non-conduction of the high-potential-side switching element on the basis of the level-shifted set signal or reset signal outputted from the pulse demodulation circuit.

2. The semiconductor device according to claim 1, wherein

the pulse modulation circuit has:

a state machine in which an internal state makes a successive transition in response to a clock input;

a first timer circuit that determines a fall timing of the data symbol; and

a second timer circuit that detects a rise of a control input signal and determine state transition timing of the state machine, and

the state machine makes a successive transition at least to a first state and a second state as determined by the second timer circuit, sends a start bit when in the first state, and sends a data bit representing a set signal or a reset signal when in the second state.

3. The semiconductor device according to claim 1, further comprising:

a level shift circuit group which is provided with a level shift circuit that outputs an input signal of a high-side region as a signal of a low-side region upon lowering a signal level, and which can implement bidirectional signal transmission.

4. The semiconductor device according to claim 2, further comprising:

a level shift circuit group which is provided with a level shift circuit that outputs an input signal of a high-side region as a signal of a low-side region upon lowering a signal level, and which can implement bidirectional signal transmission.