METHOD FOR PROCESSING DATA, FLASH MEMORY, AND TERMINAL

• US 20140321210A1
• Filed: 07/11/2014
• Published: 10/30/2014
• Est. Priority Date: 05/25/2012
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Xiang, Guangheng
• Granted Patent: US 9,281,063 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups

Abstract

Embodiments of the present invention provide a flash memory which has high operating efficiency and a longer service life, and relate to the field of electronic technologies. The flash memory includes a control circuit and a plurality of memory cells, where the memory cell is a floating-gate MOS transistor which includes a source, a gate, a drain, and a substrate; the control circuit is separately connected to the source, the gate, the drain, and the substrate and configured to output a control signal to them, so as to implement a bitwise overwrite operation on the memory cell; and the control circuit is further configured to generate a control signal when data stored by any one of the memory cells is 0, so that the memory cell overwrites the data stored by the memory cell from 0 to 1 according to the control signal.

Claims

1. A flash memory, comprising a control circuit and a plurality of memory cells, wherein:

each of the plurality of memory cells is a floating-gate Metal-Oxide-Semiconductor (MOS) transistor comprising a source, agate, a drain, and a substrate;

the control circuit is separately connected to the source, the gate, the drain, and the substrate of each memory cell and configured to output a control signal to the source, the gate, the drain, and the substrate of each memory cell, so as to implement a bitwise overwrite operation on at least one of the memory cells; and

the control circuit is further configured to generate the control signal when data stored by any one of the plurality of memory cells is 0, so that the the data stored by the memory cell is overwritten from 0 to 1 according to the control signal, wherein the control signal is configured to control the substrate of the memory cell to be grounded, the source to be connected to a negative Voltage of Programming Power (VPP), the drain to be connected to the negative VPP, and the gate to be connected to the negative VPP.

2. A flash memory, comprising a control circuit and a plurality of memory cells, wherein:

each of the plurality of memory cells is a floating-gate Metal-Oxide-Semiconductor (MOS) transistor comprising a source, agate, a drain, and a substrate;

the control circuit is configured to output a plurality of control signals to separately connect to the source, the gate, the drain, and the substrate, so as to implement a bitwise overwrite operation on the memory cell; and

the control circuit is further configured to read original data of a region to be updated in the memory cell, determine, on a bitwise basis, whether the original data is consistent with data to be written, and if inconsistent, generate a first control signal when data corresponding to a current bit of the original data is 0, so that the memory cell corresponding to the current bit overwrites data stored by the memory cell from 0 to 1, wherein the first control signal is configured to control the substrate of the memory cell to be grounded, the source to be connected to a negative Voltage of Programming Power (VPP), the drain to be connected to the negative VPP, and the gate to be connected to to the negative VPP.

3. The flash memory according to claim 2, wherein the control circuit is further configured to generate a second control signal if the data corresponding to the current bit of the original data is inconsistent with data corresponding to a current bit of the data to be written and when the data corresponding to the current bit of the original data is 1, so that the memory cell corresponding to the current bit overwrites the data stored by the memory cell from 1 to 0, wherein the second control signal is configured to control the substrate of the memory cell to be grounded, the source to be grounded, the drain to be grounded, and the gate to be connected to a VPP.

4. A terminal, comprising a flash memory comprising a control circuit and a plurality of memory cells, wherein

each of the plurality of memory cells is a floating-gate Metal-Oxide-Semiconductor (MOS) transistor comprising a source, agate, a drain, and a substrate;

the control circuit is separately connected to the source, the gate, the drain, and the substrate of each memory cell and configured to output a control signal to the source, the gate, the drain, and the substrate of each memory cell, so as to implement a bitwise overwrite operation on at least one of the memory cells; and

the control circuit is further configured to generate the control signal when data stored by any one of the plurality of memory cells is 0, so that the the data stored by the memory cell is overwritten from 0 to 1 according to the control signal, wherein the control signal is configured to control the substrate of the memory cell to be grounded, the source to be connected to a negative Voltage of Programming Power (VPP), the drain to be connected to the negative VPP, and the gate to be connected to the negative VPP.

5. A terminal, comprising a flash memory comprising a control circuit and a plurality of memory cells, wherein:

each of the plurality of memory cells is a floating-gate Metal-Oxide-Semiconductor (MOS) transistor comprising a source, agate, a drain, and a substrate;

the control circuit is configured to output a plurality of control signals to separately connect to the source, the gate, the drain, and the substrate, so as to implement a bitwise overwrite operation on the memory cell; and

the control circuit is further configured to read original data of a region to be updated in the memory cell, determine, on a bitwise basis, whether the original data is consistent with data to be written, and if inconsistent, generate a first control signal when data corresponding to a current bit of the original data is 0, so that the memory cell corresponding to the current bit overwrites data stored by the memory cell from 0 to 1, wherein the first control signal is configured to control the substrate of the memory cell to be grounded, the source to be connected to a negative Voltage of Programming Power (VPP), the drain to be connected to the negative VPP, and the gate to be connected to to the negative VPP.

6. The terminal according to claim 5, wherein the control circuit is further configured to generate a second control signal if the data corresponding to the current bit of the original data is inconsistent with data corresponding to a current bit of the data to be written and when the data corresponding to the current bit of the original data is 1, so that the memory cell corresponding to the current bit overwrites the data stored by the memory cell from 1 to 0, wherein the second control signal is configured to control the substrate of the memory cell to be grounded, the source to be grounded, the drain to be grounded, and the gate to be connected to a VPP.