HYBRID-INTEGRATED PHOTONIC CHIP PACKAGE WITH AN INTERPOSER

• US 20140321804A1
• Filed: 10/07/2013
• Published: 10/30/2014
• Est. Priority Date: 04/26/2013
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Thacker, Hiren D., Krishnamoorthy, Ashok V., Hopkins, Robert David II, Lexau, Jon, Zheng, Xuezhe, Ho, Ronald, Shubin, Ivan, Cunningham, John E.
• Granted Patent: US 9,297,971 B2
• Time in Patent Office: Days
• US Class Current: 385/14
• CPC Class Codes: G02B 6/4274 Electrical aspects G02B6/4263 and G02B6/4265 take precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/141 Disposition
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/72 Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06534 Optical coupling
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/72 : Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/37001 : Yield
• CPC Class Codes: H05K 2201/10484 : Obliquely mounted
• CPC Class Codes: H05K 3/36 : Assembling printed circuits with other printed circuits H05K7/142 takes precedence

Abstract

A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are proximate to each other in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a top surface of an interposer, and this top surface is in turn electrically coupled to a front surface of an input/output (I/O) integrated circuit that faces the top surface. Furthermore, the front surface of the I/O integrated circuit is electrically coupled to a top surface of the optical integrated circuit, where the top surface of the optical integrated circuit faces the front surface of the I/O integrated circuit.

Claims

1. A chip package, comprising:

an integrated circuit having a front surface with integrated-circuit connector pads;

integrated-circuit electrical connectors electrically coupled to the integrated-circuit connector pads;

an interposer having a top surface, facing the front surface of the integrated circuit, with first interposer connector pads, electrically coupled to the integrated-circuit electrical connectors, and second interposer connector pads;

input/output (I/O)-integrated-circuit electrical connectors electrically coupled to the second interposer connector pads;

an I/O integrated circuit having a front surface, facing the top surface, with first I/O-integrated-circuit connector pads electrically coupled to the I/O-integrated-circuit electrical connectors, and second I/O-integrated-circuit connector pads, wherein the I/O integrated circuit is proximate to the integrated circuit on a same side of the interposer, and wherein the I/O integrated circuit includes electrical I/O circuits and optical driver and receiver circuits;

optical-integrated-circuit electrical connectors electrically coupled to the second I/O-integrated-circuit connector pads; and

an optical integrated circuit having a top surface, facing the front surface of the I/O integrated circuit, with optical-integrated-circuit connector pads electrically coupled to the optical-integrated-circuit electrical connectors, wherein the optical integrated circuit is configured to communicate optical signals.

2. The chip package of claim 1, wherein the integrated circuit is adjacent to the I/O integrated circuit.

3. The chip package of claim 1, wherein the interposer further includes:

third interposer connector pads disposed on a bottom surface on an opposite side of the interposer from the top surface; and

through-substrate vias (TSVs) electrically coupling the first interposer connector pads to the third interposer connector pads, and the second interposer connector pads to the third interposer connector pads.

4. The chip package of claim 3, wherein the TSVs are configured to convey power and ground to the integrated circuit and the I/O integrated circuit.

5. The chip package of claim 3, wherein the chip package further includes:

substrate electrical connectors electrically coupled to the third interposer connector pads; and

a substrate having a front surface electrically coupled to the substrate electrical connectors.

6. The chip package of claim 5, wherein the chip package further includes a ramp-stack chip package electrically coupled to a back surface on an opposite side of the substrate from the top surface, and

wherein the ramp-stack chip package includes multiple parallel substrates arranged at an oblique angle relative to the back surface.

7. The chip package of claim 5, wherein a back surface of the optical integrated circuit on an opposite side of the optical integrated circuit from the top surface of the optical integrated circuit is coupled to the front surface of the substrate.

8. The chip package of claim 1, wherein the chip package further includes a second interposer between the front surface of the substrate and a bottom surface of the interposer on an opposite side of the interposer from the front surface of the interposer.

9. The chip package of claim 1, wherein the chip package further includes an optical fiber edge coupled to the optical integrated circuit.

10. The chip package of claim 9, wherein the optical fiber is coupled to one of:

the top surface of the optical integrated circuit; and

a back surface of the optical integrated circuit on an opposite side of the optical integrated circuit from the top surface of the optical integrated circuit.

11. The chip package of claim 1, wherein the chip package further includes an optical fiber vertically coupled to the optical integrated circuit.

12. The chip package of claim 11, wherein the optical fiber is coupled to one of:

the top surface of the optical integrated circuit; and

a back surface of the optical integrated circuit on an opposite side of the optical integrated circuit from the top surface of the optical integrated circuit.

13. The chip package of claim 1, wherein the chip package further includes an optical source optically coupled to the optical integrated circuit.

14. The chip package of claim 1, wherein the interposer includes one of:

a ceramic, an organic material, a glass, and a semiconductor.

15. The chip package of claim 1, wherein the chip package further includes a thermal-cooling mechanism on a back surface of the integrated circuit on an opposite side of the integrated circuit from the front surface of the integrated circuit.

16. A system, comprising:

a processor;

a memory coupled to the processor; and

a chip package, wherein the chip package includes;

an integrated circuit having a front surface with integrated-circuit connector pads;

integrated-circuit electrical connectors electrically coupled to the integrated-circuit connector pads;

an interposer having a top surface, facing the front surface of the integrated circuit, with first interposer connector pads, electrically coupled to the integrated-circuit electrical connectors, and second interposer connector pads;

input/output (I/O)-integrated-circuit electrical connectors electrically coupled to the second interposer connector pads;

an I/O integrated circuit having a front surface, facing the top surface, with first I/O-integrated-circuit connector pads electrically coupled to the I/O-integrated-circuit electrical connectors, and second I/O-integrated-circuit connector pads, wherein the I/O integrated circuit is proximate to the integrated circuit on a same side of the interposer, and wherein the I/O integrated circuit includes electrical I/O circuits and optical driver and receiver circuits;

optical-integrated-circuit electrical connectors electrically coupled to the second I/O-integrated-circuit connector pads; and

an optical integrated circuit having a top surface, facing the front surface of the I/O integrated circuit, with optical-integrated-circuit connector pads electrically coupled to the optical-integrated-circuit electrical connectors, wherein the optical integrated circuit is configured to communicate optical signals.

17. The system of claim 16, wherein the interposer further includes:

third interposer connector pads disposed on a bottom surface on an opposite side of the interposer from the top surface; and

through-substrate vias (TSVs) electrically coupling the first interposer connector pads to the third interposer connector pads, and the second interposer connector pads to the third interposer connector pads.

18. The system of claim 17, wherein the chip package further includes:

substrate electrical connectors electrically coupled to the third interposer connector pads; and

a substrate having a front surface electrically coupled to the substrate electrical connectors.

19. The system of claim 18, wherein the chip package further includes a ramp-stack chip package electrically coupled to a back surface on an opposite side of the substrate from the top surface, and

wherein the ramp-stack chip package includes multiple parallel substrates arranged at an oblique angle relative to the back surface.

20. A method for communicating electrical signals between an integrated circuit and an optical integrated circuit, wherein the method comprises:

coupling the electrical signals from integrated-circuit connector pads on a front surface of the integrated circuit to first interposer connector pads on a top surface of an interposer via integrated-circuit electrical connectors, wherein the front surface faces the top surface;

conveying the electrical signals via traces disposed on the interposer, wherein the traces electrically couple the first interposer connector pads and second interposer connector pads on the top surface;

coupling the electrical signals from the second interposer connector pads to first input/output (I/O)-integrated-circuit connector pads on a front surface of an I/O integrated circuit via I/O-integrated-circuit electrical connectors;

conveying the electrical signals via traces disposed on the I/O integrated circuit, wherein the traces electrically couple the first I/O-integrated-circuit connector pads and second I/O-integrated-circuit connector pads on the front surface; and

coupling the electrical signals from the second I/O-integrated-circuit connector pads to optical-integrated-circuit connector pads on a top surface of an optical integrated circuit via optical-integrated-circuit electrical connectors.