FLEXIBLE ALLOCATION OF I/O CHANNELS OF A HARDWARE COMPONENT

• US 20140324408A1
• Filed: 10/16/2013
• Published: 10/30/2014
• Est. Priority Date: 04/29/2013
• Status: Active Grant

• Current Assignee: Dspace GmbH
• Original Assignee: Dspace Digital Signal Processing And Control Engineering Gmbh
• Inventors: MERTEN, Stefan, SCHLENGER, Marc, ROSS, Holger, MERTENS, Frank
• Granted Patent: US 9,811,361 B2
• Time in Patent Office: Days
• US Class Current: 703/21
• CPC Class Codes: G06F 15/7871 Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 8/35 model driven
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines

Abstract

A method for generating software for a hardware component of a measuring, control, or regulating system having a processor, an FPGA, and a plurality of I/O channels. The I/O channels are connected to the FPGA and the FPGA is connected to the processor via a communications interface. The method includes the steps of selecting a first subset of the I/O channels for operation by the FPGA, generating a first application for execution in the FPGA, selecting a second subset of the I/O channels for operation by the processor, and generating a second application for execution on the processor. The step of generating a first application comprises generating code for connecting the second subset of I/O channels to the communications interface. The invention relates in addition to a method for operating a hardware component.

Claims

1. A method for generating software for a hardware component of a measuring, control, or regulating system having a processor, an FPGA (Field Programmable Gate Array), and a plurality of I/O (Input/Output) channels, the I/O channels being connectable to the FPGA and the FPGA being connectable to the processor via a communications interface, the method comprising:

selecting a first subset of I/O channels for operation by the FPGA;

generating a first application for execution in the FPGA;

selecting a second subset of I/O channels for operation by the processor; and

generating a second application for execution on the processor,

wherein the step of generating a first application comprises the generation of code for connecting the second subset of I/O channels to the communications interface.

2. The method according to claim 1, wherein the step of generating code for connecting the second subset of I/O channels to the communications interface comprises the generation of code for executing a signal processing between at least one of the I/O channels of the second subset and the communications interface.

3. The method according to claim 1, further comprising generating an application model, wherein the step of generating the first application comprises the model-based automatic generation of code.

4. The method according to claim 3, wherein the step of generating code for connecting the second subset of I/O channels to the communications interface comprises the automatic generation of code for connecting I/O channels that are part of the second subset of I/O channels.

5. The method according to claim 3, wherein the step of generating code for connecting the second subset of I/O channels to the communications interface comprises providing pre-synthesized code for connecting I/O channels that are part of the second subset of I/O channels.

6. The method according to claim 3, wherein the step of generating the first application comprises providing identification information of I/O channels of the first subset.

7. The method according to claim 3, wherein the step of generating the first application comprises receiving identification information of I/O channels of the second subset.

8. The method according to claim 1, further comprising generating an application model, wherein the step of generating the second application comprises the model-based automatic generation of code.

9. The method according to claim 8, wherein the step of generating the second application comprises providing identification information of I/O channels of the second subset.

10. The method according to claim 8, wherein the step of generating the second application comprises receiving identification information of I/O channels of the first subset.

11. A method for operating a hardware component of a measuring, control, or regulating system having a processor, an FPGA, and a plurality of I/O channels, wherein the I/O channels are connectable to the FPGA and the FPGA is connectable to the processor via a communications interface, the method comprising:

loading software that is generated according to the method according to claim 1; and

executing the software,

wherein the loading of the software comprises loading of the first application into the FPGA and loading of the second application into the processor.

12. The method according to claim 11, further comprising partial reconfiguration of the FPGA.

13. A hardware component of a measuring, control, or regulating system having a processor, an FPGA, and a plurality of I/O channels, wherein the I/O channels are connectable to the FPGA and the FPGA is connectable to the processor via a communications interface, and wherein the hardware component is configured to perform the method according to claim 11.

14. A computer program product having computer implemented instructions, which after loading and execution in a data processing device performs the method according to claim 1.

15. A digital storage medium having electronically readable control signals, which operates together with a programmable data processing device so that the method according to claim 1 is performed in a data processing device.