DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

• US 20140325118A1
• Filed: 07/05/2013
• Published: 10/30/2014
• Est. Priority Date: 04/30/2013
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Cheng, Kuo-Yi, Lin, Wei, Wong, Kim-Hon, Chang, Chun-Yen, Lee, Hao-Zhi, Lin, Hung-Chun
• Granted Patent: US 9,703,698 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

A data writing method for writing data into a physical erasing unit and a memory controller and a memory storage apparatus using the data writing method are provided. The method includes dividing the data into a plurality of information frames in a unit of one physical programming unit. The method also includes writing the information frames in sequence into at least one physical programming unit constituted by memory cells disposed on at least one first word line and programming the storage state of memory cells disposed on at least one second word line following the first word line to an auxiliary pattern. Accordingly, the method effectively prevents data stored in the physical erasing unit, which is not full of data, from being lost due to a high temperature.

Claims

1. A data writing method, for writing data into a physical erasing unit comprising a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, wherein each of the memory cells electrically connected to one of the word lines and one of the bit lines, the memory cells constitute a plurality of physical programming units comprising a plurality of lower physical programming units and a plurality of upper physical programming units, and a speed of writing data into the lower physical programming units is higher than a speed of writing data into the upper physical programming units, the data writing method comprising:

dividing the data into a plurality of information frames in a unit of one physical programming unit, wherein the number of the information frames is smaller than the number of the physical programming units of the physical erasing unit; and

filling the lower physical programming units with the information frames and then writing the rest of the information frames to the upper physical programming units, or programming an auxiliary pattern into the memory cells on at least one second word line, wherein the at least one second word line is adjacent to at least one first word line among the word lines, and the at least one first word line stores at least a portion of the information frames, and the auxiliary pattern is invalid data,

wherein, in the physical erasing unit, the at least one first word line is not adjacent to a third word line, and a storage state of the memory cells on the third word line is an erasing state.

2. The data writing method according to claim 1, wherein a storage state of each of the memory cells is available to be interpreted as a first storage state, a second storage state, a third storage state, or a fourth storage state, wherein a verification voltage corresponding to the first storage state is lower than a verification voltage corresponding to the second storage state, the verification voltage corresponding to the second storage state is lower than a verification voltage corresponding to the third storage state, and the verification voltage corresponding to the third storage state is lower than a verification voltage corresponding to the fourth storage state,

wherein the step of programming the auxiliary pattern into the memory cells on at least one second word line comprises:

writing the information frames in sequence into at least one physical programming unit constituted by the memory cells on the at least one first word line; and

programming the memory cells on the at least one second word line to the second storage state or the third storage state.

3. The data writing method according to claim 1, wherein the step of programming the auxiliary pattern into the memory cells on at least one second word line comprises:

setting the auxiliary pattern according to the storage state of the memory cells on the at least one first word line; and

programming the auxiliary pattern into the memory cells on at least one second word line.

4. The data writing method according to claim 3, wherein the step of programming the auxiliary pattern into the memory cells on at least one second word line comprises:

programming the memory cells on the at least one second word line to the same storage state as the memory cells on the last word line among the at least one first word line.

5. The data writing method according to claim 1, wherein the step of filling the lower physical programming units with the information frames and then writing the rest of the information frames to the upper physical programming units comprises:

writing a portion of the information frames into the physical erasing unit to fill the lower physical programming units; and

writing the rest of the information frames to the upper physical programming units of the physical erasing unit after the lower physical programming units are filled.

6. The data writing method according to claim 1, wherein the step of programming the auxiliary pattern into the memory cells on at least one second word line comprises:

programming a random value to the memory cells on the at least one second word line.

7. The data writing method according to claim 6, wherein a potential of the storage state of each memory cell on the at least one second word line is not greater than a potential of the storage state of the corresponding memory cell on the at least one first word line.

8. The data writing method according to claim 6, wherein a potential of the storage state of each memory cell on the at least one second word line is not greater than a middle value between a potential of the first storage state and a potential of the storage state of the corresponding memory cell on the at least one first word line.

9. A memory controller for controlling a rewritable non-volatile memory module, the memory controller comprising:

a host interface configured to be coupled to a host system;

a memory interface configured to be coupled to the rewritable non-volatile memory module; and

a memory management circuit coupled to the host interface and the memory interface and configured to write data into a physical erasing unit of the rewritable non-volatile memory module, wherein the physical erasing unit comprises a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, each of the memory cells is electrically connected to one of the word lines and one of the bit lines, the memory cells constitute a plurality of physical programming units comprising a plurality of lower physical programming units and a plurality of upper physical programming units, and a speed of writing data is written into the lower physical programming units is higher than a speed of writing data into the upper physical programming units,

wherein the memory management circuit divides the data into a plurality of information frames in a unit of one physical programming unit, and the number of the information frames is smaller than the number of the physical programming units of the physical erasing unit,

wherein the memory management circuit fills the lower physical programming units with the information frames and then writes the rest of the information frames to the upper physical programming units, or programs an auxiliary pattern into at least one second word line to, wherein the at least one second word line is adjacent to at least one first word line among the word lines, and the at least one first word line stores at least a portion of the information frames and the auxiliary pattern is invalid data, wherein, in the physical erasing unit, the at least one first word line is not adjacent to a third word line, and a storage state of the memory cells on the third word line is an erasing state.

10. The memory controller according to claim 9, wherein a storage state of each of the memory cells is available to be interpreted as a first storage state, a second storage state, a third storage state, or a fourth storage state, wherein a verification voltage corresponding to the first storage state is lower than a verification voltage corresponding to the second storage state, the verification voltage corresponding to the second storage state is lower than a verification voltage corresponding to the third storage state, and the verification voltage corresponding to the third storage state is lower than a verification voltage corresponding to the fourth storage state,

wherein, in said operation of programming the auxiliary pattern into the at least one second word line, the memory management circuit writes the information frames in sequence into at least one physical programming unit constituted by the memory cells on the at least one first word line, and programs the memory cells on the at least one second word line to the second storage state or the third storage state.

11. The memory controller according to claim 9, wherein the memory management circuit sets the auxiliary pattern according to the storage state of the memory cells on the at least one first word line.

12. The memory controller according to claim 11, wherein the auxiliary pattern is the same as the storage state of the memory cells on the last word line among the at least one first word line.

13. The memory controller according to claim 9, wherein, in said operation of filling the lower physical programming units with the information frames and then writing the rest of the information frames to the upper physical programming units, the memory management circuit writes a portion of the information frames into the physical erasing unit to fill the lower physical programming units;

and writing the rest of the information frames to the upper physical programming units of the physical erasing unit after the lower physical programming units are filled.

14. The memory controller according to claim 9, wherein, in said operation of programming the auxiliary pattern into the memory cells on the at least one second word line, the memory management circuit programs a random value to the memory cells on the at least one second word line.

15. The memory controller according to claim 9, wherein a potential of the storage state of each memory cell on the at least one second word line is not greater than a potential of the storage state of the corresponding memory cell on the at least one first word line.

16. The memory controller according to claim 9, wherein a potential of the storage state of each memory cell on the at least one second word line is not greater than a middle value between a potential of the first storage state and a potential of the storage state of the corresponding memory cell on the at least one first word line.

17. A memory storage apparatus, comprising:

a connector configured to be coupled to a host system;

a rewritable non-volatile memory module; and

a memory controller coupled to the connector and the rewritable non-volatile memory module and configured to write data into a physical erasing unit of the rewritable non-volatile memory module, wherein the physical erasing unit comprises a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, each of the memory cells is electrically connected to one of the word lines and one of the bit lines, the memory cells constitute a plurality of physical programming units comprising a plurality of lower physical programming units and a plurality of upper physical programming units, and a speed of writing data into the lower physical programming units is higher than a speed of writing data into the upper physical programming units,

wherein the memory controller divides the data into a plurality of information frames in a unit of one physical programming unit, and the number of the information frames is smaller than the number of the physical programming units of the physical erasing unit,

wherein the memory controller writes the information frames in sequence into at least one physical programming unit constituted by the memory cells on at least one first word line among the words line of the physical erasing unit,

wherein the memory controller fills the lower physical programming units with the information frames and then writes the rest of the information frames to the upper physical programming units, or programs an auxiliary pattern into the memory cells on at least one second word line, wherein the at least one second word line is adjacent to at least one first word line among the word lines, and the at least one first word line stores at least a portion of the information frames and the auxiliary pattern is invalid data, wherein, in the physical erasing unit, the at least one first word line is not adjacent to a third word line, and a storage state of the memory cells on the third word line is an erasing state.

18. The memory storage apparatus according to claim 17, wherein a storage state of each of the memory cells is available to be interpreted as a first storage state, a second storage state, a third storage state, or a fourth storage state, wherein a verification voltage corresponding to the first storage state is lower than a verification voltage corresponding to the second storage state, the verification voltage corresponding to the second storage state is lower than a verification voltage corresponding to the third storage state, and the verification voltage corresponding to the third storage state is lower than a verification voltage corresponding to the fourth storage state,

wherein, in an operation of programming the auxiliary pattern into the memory cells on the at least one second word line, the memory controller writes the information frames in sequence into at least one physical programming unit constituted by the memory cells on the at least one first word line, and programs the memory cells on the at least one second word line to the second storage state or the third storage state.

19. The memory storage apparatus according to claim 17, wherein the memory controller sets the auxiliary pattern according to the storage state of the memory cells on the at least one first word line.

20. The memory storage apparatus according to claim 19, wherein the auxiliary pattern is the same as the storage state of the memory cells on the last word line among the at least one first word line.

21. The memory storage apparatus according to claim 17, wherein, in an operation of filling the lower physical programming units with the information frames and then writing the rest of the information frames to the upper physical programming units, the memory controller writes a portion of the information frames into the physical erasing unit to fill the lower physical programming units;

and writing the rest of the information frames to the upper physical programming units of the physical erasing unit after the lower physical programming units are filled.

22. The memory storage apparatus according to claim 17, wherein, in the operation of programming the auxiliary pattern into the memory cells on the at least one second word line, the memory controller programs a random value to the memory cells on the at least one second word line.

23. The memory storage apparatus according to claim 17, wherein a potential of the storage state of each memory cell on the at least one second word line is not greater than a potential of the storage state of the corresponding memory cell on the at least one first word line.

24. The memory storage apparatus according to claim 17, wherein the potential of the storage state of each memory cell on the at least one second word line is not greater than a middle value between a potential of the first storage state and the potential of the storage state of the corresponding memory cell on the at least one first word line.

25. A memory storage apparatus, comprising:

a connector configured to be coupled to a host system;

a rewritable non-volatile memory module comprising a plurality of physical erasing units, wherein each of the physical erasing units comprises a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, each of the memory cells is electrically connected to one of the word lines and one of the bit lines, and the memory cells constitute a plurality of physical programming units; and

a memory controller coupled to the connector and the rewritable non-volatile memory module;

wherein a second word line of one physical erasing unit among the physical erasing units stores invalid data, and the invalid data is the same as valid data on a first word line adjacent to the second word line, or the invalid data is in a non-erasing state.