MEMORY SYSTEM AND METHOD FOR OPERATING A MEMORY SYSTEM

• US 20140325124A1
• Filed: 04/09/2014
• Published: 10/30/2014
• Est. Priority Date: 04/30/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Antonakopoulos, Theodore, Papandreou, Nikolaos, Pozidis, Charalampos
• Granted Patent: US 9,672,910 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1003 Interface circuits for daisy chain or ring bus memory arrangements
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A memory system for storing data in a plurality N of memory chips. The memory system includes a number K of sets of memory chips, wherein each set of the K sets includes a number M of the memory chips, with N=K·M; and one signal processing unit having a number L of signal processing engines for signal processing data of the N memory chips and having a data link interface for interfacing each of the K sets.

Claims

1. A memory system for storing data in a plurality N of memory chips, the memory system comprising:

a number K of sets of memory chips, wherein each set of the K sets includes a number M of the memory chips, with N=K·

M; and

one signal processing unit having a number L of signal processing engines for signal processing data of the N memory chips and having a data link interface for interfacing each of the K sets.

2. The memory system according to claim 1, wherein the data link interface includes K interface transceivers, and a respective one of the K interface transceivers is allocated to a respective one of the K sets.

3. The memory system according to claim 2, wherein each memory chip of the N memory chips has a single data link chip transceiver.

4. The memory system according to claim 3, wherein each of the N data link chip transceivers is configured to send data to one of a N-1 other data link chip transceivers or to one of the K interface transceivers, to receive data from one of the N-1 other data link chip transceivers or from one of the K interface transceivers, and to pass through received data to one of the N-1 other data link chip transceivers or to one of the K interface transceivers.

5. The memory system according to claim 1, wherein for each of the K sets, the M memory chips of one set and the data link interface of the signal processing unit form a ring network for data transmissions.

6. The memory system according to claim 1, wherein the data link interface includes K interface transceivers, wherein a respective one of the K interface transceivers is allocated to a respective one of the K sets, and wherein for each of the K sets, the M memory chips of the set and the allocated interface transceiver form a ring network for data transmissions.

7. The memory system according to claim 1, wherein for each of the K sets, the memory chips and the L signal processing engines form a ring network for data transmissions.

8. The memory system according to claim 1, wherein for each of the K sets, the M memory chips of the set and the L signal processing engines are coupled by a first interconnect and a second interconnect, wherein the first interconnect is adapted to interface outputs of the memory chips with inputs of the signal processing engines, and wherein the second interconnect is adapted to interface the inputs of the memory chips with the outputs of the signal processing engines.

9. The memory system according to claim 8, wherein each of the first and second interconnects includes a single serial Tx/Rx link or is configured to switch over multiple Tx/Rx links.

10. The memory system according to claim 8, further comprising:

a controller including a first controller to control the first interconnect and a second controller to control the second interconnect.

11. The memory system according to claim 10, wherein, for each couple of an output of a memory chip and an input of a signal processing engine, the first controller is adapted to adjust a number of lanes connecting the output of the memory chip with the input of the signal processing engine, and wherein for each couple of an input of the memory chip and an output of the signal processing engine, the second controller is adapted to adjust a number of lanes connecting the input of the memory chip with the output of the signal processing engine.

12. The memory system according to claim 1, wherein the memory chips are multi-level memory chips having a plurality of programmable levels, in particular PCM chips or RRAM chips.

13. The memory system according to claim 1, wherein the signal processing unit is embodied as a CODEC unit and the signal processing engine is embodied as a CODEC engine.

14. The memory system according to claim 6, wherein the K interface transceivers are embodied as K high-speed data link transceivers.

15. A method of operating a memory system for storing data in a plurality N of memory chips, wherein the memory system includes the N memory chips and one signal processing unit having a number L of signal processing engines for signal processing the data of the N memory chips, the method comprising:

grouping the N memory chips into a number K of sets of memory chips, with N=K·

M; and

interfacing each of the K sets with the signal processing unit by means of a data link interface.