TIMING CONTROL CIRCUIT

• US 20140325253A1
• Filed: 02/11/2014
• Published: 10/30/2014
• Est. Priority Date: 04/26/2013
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: OGATA, Yuuki, Koyanagi, Yoichi
• Granted Patent: US 9,684,332 B2
• Time in Patent Office: Days
• US Class Current: 713/601
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A timing control circuit includes: a first variable delay circuit configured to receive first data having a first communication speed, and to give a variable delay to the first data; a first multiplexer configured to receive output of the first variable delay circuit, and to convert into second data having a second communication speed different from the first communication speed in accordance with first control signal; a second variable delay circuit configured to receive third data having the first communication speed, and to give a delay corresponding to the delay of the first variable delay circuit to the third data; a decision circuit configured to compare timings of output of the second variable delay circuit and the first control signal; and a control circuit configured to control the delays of the first variable delay circuit and the second variable delay circuit in accordance with output of the decision circuit.

Claims

1. A timing control circuit, comprising:

a first variable delay circuit configured to receive first data having a first communication speed, and to give a variable delay to the first data;

a first multiplexer configured to receive output of the first variable delay circuit, and to convert, based on first control signal, into second data having a second communication speed different from the first communication speed;

a second variable delay circuit configured to receive third data having the first communication speed, and to give a delay corresponding to the delay of the first variable delay circuit to the third data;

a decision circuit configured to compare timings of output of the second variable delay circuit and the first control signal; and

a control circuit configured to control the delays of the first variable delay circuit and the second variable delay circuit in accordance with output of the decision circuit.

2. The timing control circuit according to claim 1,

wherein the first variable delay circuit includes a number of variable delay units corresponding to the first data, and

the second variable delay circuit includes a same circuit configuration as that of the variable delay unit.

3. The timing control circuit according to claim 2,

wherein the variable delay units include

a plurality of delay elements configured to give different delays to the first data, respectively, and

a selector configured to select any one of data provided with the different delays to the first data.

4. The timing control circuit according to claim 3,

wherein the selector is configured to select any one of the data provided with the different delays to the first data in accordance with output of the control circuit.

5. The timing control circuit according to claim 2,

wherein switching of delays to be given to the first data by the variable delay unit is performed at a different timing from a timing of fetching output of the variable delay unit by the first multiplexer.

6. The timing control circuit according to claim 5,

wherein the switching of delays to be given to the first data by the variable delay unit is performed at different timing from timing of taking in output of the variable delays unit by the first multiplexer by 90°

or 180°

.

7. The timing control circuit according to claim 1,

wherein the second communication speed is two times the first communication speed.

8. The timing control circuit according to claim 7,

wherein the third data has a repetition pattern of a high level “

1” and

a low level “

0”

.

9. The timing control circuit according to claim 8, further comprising

a pattern generation circuit configured to generate the third data.

10. The timing control circuit according to claim 9,

wherein the pattern generation circuit includes a selector configured to alternately select and output fixed input “

0” and

“

1”

in accordance with the first communication speed.

11. The timing control circuit according to claim 7, further comprising

a third multiplexer configured to convert parallel data two times the first data into the first data in accordance with a second control signal.

12. The timing control circuit according to claim 11,

wherein the second control signal is a signal having half the frequency of the first control signal.

13. The timing control circuit according to claim 1,

wherein the timing control circuit is a parallel-serial conversion circuit configured to convert a plurality of parallel data into serial data, and to output the data.