Removable indicator structure in electronic chips of a common substrate for process adjustment

• US 20140327003A1
• Filed: 05/03/2013
• Published: 11/06/2014
• Est. Priority Date: 05/03/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: FUERGUT, Edward, Escher-Poeppel, Irmgard, Engelhardt, Manfred, Timme, Hans-Joerg, Eder, Hannes
• Granted Patent: US 9,275,916 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/67069 for drying etching
• CPC Class Codes: H01L 21/67253 Process monitoring, e.g. flow or thickness monitoring
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/784 the substrate being a semiconductor body
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/24 Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change voltage contrast G01R31/311
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 22/30 Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A method of processing a plurality of packaged electronic chips being connected to one another in a common substrate is provided, wherein the method comprises etching the electronic chips, detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure, and adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.

Claims

1. A method of processing a plurality of packaged electronic chips being connected to one another in a common substrate, the method comprising:

etching the electronic chips;

detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure; and

adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.

2. The method according to claim 1, wherein detecting information comprises analyzing volatile matter in an environment of the electronic chips which volatile matter is impacted by an etching product generated by removing material of the indicator structure from the electronic chips by the etching.

3. The method according to claim 2, wherein the analyzed volatile matter is plasma used for plasma etching and being modified by the at least partial removal of the indicator structure.

4. The method according to claim 3, wherein analyzing the plasma is performed by at least one of the group consisting of Optical Emission Spectroscopy, and Coherent Anti Stokes Raman Scattering.

5. The method according to claim 2, wherein the analyzed volatile matter is effluent gas generated when removing material of the indicator structure by plasma etching.

6. The method according to claim 5, wherein analyzing the effluent gas is performed by at least one of the group consisting of Optical Emission Spectroscopy, and Mass Spectroscopy.

7. The method according to claim 1, wherein the indicator structure comprises one of the group consisting of dopant, implanted material, and a deposited layer.

8. The method according to claim 1, wherein the etching is a selective etching so that an etching rate of material of the indicator structure is different from an etching rate of material next to the indicator structure.

9. The method according to claim 1, wherein the plurality of packaged electronic chips being connected to one another in the common substrate comprise a semiconductor wafer being divided into the electronic chips by mold structures as package.

10. The method according to claim 1, wherein adjusting the processing comprises at least one of the group consisting of stopping the etching, modifying an etching rate, modifying an etch parameter, modifying the etch process, and continuing the etching with the same etch conditions or with modified etch conditions for a predefined additional etching time interval.

11. The method according to claim 1, wherein the indicator structure is a continuous or discontinuous indicator layer embedded at a constant depth level within all electronic chips.

12. The method according to claim 1, comprising:

stopping the etching;

subsequently singularizing the electronic chips.

13. A method of processing a plurality of electronic chips being connected to one another by a common substrate, the method comprising:

plasma etching the electronic chips simultaneously;

detecting volatile matter in an environment of the plasma-etched electronic chips to thereby derive information indicative of an exposure of an indicator layer embedded within the electronic chips and being exposed after the etching has removed chip material above the indicator layer, wherein the volatile matter is impacted by the exposure of the indicator layer; and

adjusting the plasma etching upon detecting the exposure of the indicator layer.

14. The method according to claim 13, wherein processing the plurality of electronic chips comprises processing a plurality of electronic chips being packaged by a mold structure.

15. A device for processing a plurality of packaged electronic chips being connected to one another in a common substrate, the device comprising:

etching means configured for etching the electronic chips;

detection means configured for detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure; and

control means being supplied with the detected information and being configured for adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.

16. The device according to claim 15, wherein the detection means are configured for detecting the information by analyzing volatile matter in an environment of the electronic chips which volatile matter is impacted by an etching product generated by removing material of the indicator structure from the electronic chips by the etching.

17. The device according to claim 16, wherein the analyzed volatile matter is plasma used for plasma etching and being modified by the least partial removal of the indicator structure.

18. The device according to claim 16, wherein the analyzed volatile matter is effluent gas generated when removing material of the indicator structure by plasma etching.

19. A device for processing a plurality of electronic chips being connected to one another by a common substrate, the device comprising:

a plasma etching unit configured for plasma etching the electronic chips simultaneously;

a detection unit configured for detecting volatile matter in an environment of the plasma-etched electronic chips to thereby derive information indicative of an exposure of an indicator layer embedded within the electronic chips and being exposed after the etching has removed chip material above the indicator layer, wherein the volatile matter is impacted by the exposure of the indicator layer; and

a control unit being supplied with the information and being configured for adapting the processing upon detecting the exposure of the indicator layer.

20. An article, comprising:

a substrate;

a plurality of electronic chips being connected to one another within the substrate;

an indicator layer embedded within the electronic chips;

wherein the indicator layer is configured to be at least partially removable from the electronic chips by plasma etching so that its plasma etching product impacts volatile matter in an environment of the electronic chips so that the exposure of the indicator layer is detectable by analyzing the volatile matter.

21. The article according to claim 20, comprising a mold structure by which the plurality of electronic chips are packaged.

22. The article according to claim 20, wherein the substrate comprises a plate-shaped wafer comprising the plurality of electronic chips as sections of the wafer.

23. The article according to claim 20, wherein the substrate is a plate-shaped mold structure comprising a plurality of recesses each accommodating a respective one of the plurality of electronic chips.

24. The article according to claim 20, wherein the substrate is a plate-shaped mold structure comprising a recess accommodating a wafer comprising the plurality of electronic chips as sections of the wafer.

25. An electronic chip, comprising:

a semiconductor substrate;

at least one integrated circuit component being integrated in the semiconductor substrate;

an indicator layer forming an exterior surface portion of the semiconductor substrate, wherein the indicator layer is configured to be at least partially removable by plasma etching so that its plasma etching product impacts volatile matter in an environment of the semiconductor substrate so that the exposure of the indicator layer is detectable by analyzing the volatile matter;

a mold structure covering at least a part of the semiconductor substrate.