MAGNETIC MEMORY DEVICES

• US 20140328116A1
• Filed: 05/02/2014
• Published: 11/06/2014
• Est. Priority Date: 05/06/2013
• Status: Active Grant

• Current Assignee: T3Memory USA, Inc.
• Original Assignee: T3Memory USA, Inc.
• Inventors: Guo, Yimin
• Granted Patent: US 11,271,034 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

A STT-MRAM comprises apparatus and a method of manufacturing a plurality of magnetoresistive memory element having a dielectric thermal buffer layer between a thin top electrode of the MTJ element and a bit line, and a bit-line VIA electrically connecting the top electrode and the bit line having a vertical distance away from the location of the MTJ stack. In a laser thermal annealing, a short wavelength of a laser has a shallow thermal penetration depth and a high thermal resistance from the bit line to the MTJ stack only causes a temperature rise of the MTJ stack being much smaller than that of the bit line. As the temperature of the MTJ element during the laser thermal annealing of bit line copper layer is controlled under 300-degree C., possible damages on MTJ and magnetic property can be avoided.

Claims

1. A spin-transfer torque magnetoresistive memory comprising a control circuitry and at least one memory cell comprising:

a bottom electrode provided on a surface of a substrate connecting to a VIA of a select transistor;

a patterned MTJ stack consisting of a seed layer provided on the top surface of the bottom electrode, an MTJ multilayer provided on the top surface of the seed layer and a cap layer provided on the top surface of the MTJ multilayer;

a top electrode provided on the surface of the MTJ stack;

a dielectric thermal barrier layer provided on the top surface of the top electrode;

a bit-line VIA provided on the surface of the top electrode and surrounded by the dielectric thermal barrier layer and having a vertical distance away from the MTJ stack;

a bit line provided on the top surface of the dielectric thermal barrier layer and electrically connecting to the bit-line VIA.

2. The element of claim 1, wherein said insulating thermal barrier layer is made of an oxide, or nitride, or oxynitride having a low thermal conductivity.

3. The element of claim 1, wherein said insulating thermal barrier layer is preferred to be made of an oxide, or nitride, selected from the stoichiometric composition group of Al2O3, SiO2, Si3N4, MgO.

4. The element of claim 1, wherein said insulating thermal barrier layer has a thickness in a range from 50 nm to 500 nm.

5. The element of claim 1, wherein said bit line layer is made of a copper or CuAl line having a seed layer such as TiN, TaN, etc. and is encapsulated by a SiNx layer.

6. The element of claim 1, wherein said bit line layer is thermal annealed by a pulsed short wavelength laser.

7. The element of claim 1, wherein said bit line layer has a thickness in a range from 50 nm to 500 nm.

8. The element of claim 1, wherein said top electrode layer is made by a multilayer of Ta/Ru/Ta.

9. The element of claim 1, wherein said top electrode layer has a thickness in a range from 20 nm to 200 nm.

10. The element of claim 1, wherein said vertical distance between said bit-line VIA and said MTJ stack is least 20 nm, preferred to be more than 100 nm.

11. The element of claim 1, wherein said MTJ multilayer further consisting of a recording layer, a tunneling barrier and a reference layer

12. The element of claim 11, wherein said tunnel barrier layer is made of a metal oxide or a metal nitride, a metal oxynitride, preferred to be MgO, ZnO, MgZnO, MgN, MgON.

13. The element of claim 1, wherein said recording layer and said reference layer are ferromagnetic layers.

14. A method of manufacturing a magnetoresistive memory element comprising:

deposit and pattern a bottom electrode on a surface of a substrate connecting to a VIA of a select transistor;

deposit and pattern a MTJ stack consisting of a seed layer, an MTJ multilayer and a cap layer;

refill a dielectric layer surrounding the MTJ stack and conduct a CMP process to flatten the top surface;

deposit and pattern a top electrode on the surface of the MTJ stack and surrounding dielectric layer;

deposit a dielectric thermal barrier layer on the top surface of the top electrode;

open a bit-line VIA in the dielectric thermal barrier layer on the surface of the top electrode and having a vertical distance away from the MTJ stack;

deposit a seed layer and electroplate a bit line in the bit-line VIA and on the top surface of the dielectric thermal barrier layer;

conduct a CMP process to flatten the top surface of the bit line and followed by a deposition of a dielectric protective layer;

conduct a pulsed short wavelength laser thermal annealing on the bit line.

15. The element of claim 14, wherein said laser thermal annealing generates a temperature rise of said bit line above 400-degree C.

16. The element of claim 14, wherein during said laser thermal annealing, the maximum temperature rise of said MTJ stack is below 300-degree C.