METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS

• US 20140329388A1
• Filed: 05/01/2013
• Published: 11/06/2014
• Est. Priority Date: 05/01/2013
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation
• Inventors: Jang, Linus, Seo, Soon-Cheon, Jung, Ryan O.
• Granted Patent: US 9,214,360 B2
• Time in Patent Office: Days
• US Class Current: 438/702
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/28141 insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer.

Claims

1. A method, comprising:

forming a layer of material above a semiconductor substrate;

forming a masking layer above said layer of material, wherein said masking layer is comprised of a first plurality features positioned above a first region of said semiconductor substrate and a second plurality of features positioned above a second region of said semiconductor substrate, wherein said first and second plurality of features have the same pitch spacing and wherein said first and second plurality of features have different widths; and

performing at least one etching process on said layer of material through said masking layer.

2. The method of claim 1, wherein said first and second plurality of spacers are comprised of at least one sidewall spacer.

3. The method of claim 1, wherein said first plurality of features has a width that is less than a width of said second plurality of features.

4. The method of claim 1, wherein said first plurality of features has a width that is greater than a width of said second plurality of features.

5. The method of claim 1, wherein said layer of material is a layer of hard mask material.

6. The method of claim 1, wherein forming said layer of material comprises forming said layer of material above a layer of gate electrode material.

7. The method of claim 1, wherein performing said at least one etching process on said layer of material through said masking layer results in the formation of a patterned layer of material comprised of a first plurality of layer features positioned above said first region of said semiconductor substrate and a second plurality of layer features positioned above said second region of said semiconductor substrate, wherein said first and second plurality of layer features have said same pitch spacing and wherein said first and second plurality of layer features have different widths.

8. The method of claim 7, further comprising:

removing said etch mask; and

performing an etching process on an underlying layer of material through said patterned layer of material.

9. A method, comprising:

forming a layer of material above a semiconductor substrate;

performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers above said layer of material, wherein said first plurality of spacers are positioned above a first region of said semiconductor substrate and said second plurality of spacers are positioned above a second region of said semiconductor substrate, wherein said first and second plurality of spacers have a same initial width and a same pitch spacing;

forming a masking layer that covers said first plurality of spacers but exposes said second plurality of spacers for further processing; and

performing a second sidewall image transfer process to form additional spacers adjacent each of said second plurality of spacers so as to result in a plurality of combined spacer structures positioned above said second region, wherein said combined spacer structures have a combined width that is greater than said initial width and wherein said first plurality of spacers and said plurality of combined spacer structures define an etch mask.

10. The method of claim 9, further comprising:

removing said masking layer; and

performing at least one etching process on said layer of material through said etch mask.

11. The method of claim 9, wherein said layer of material is a layer of hard mask material.

12. The method of claim 9, wherein forming said layer of material comprises forming said layer of material above a layer of gate electrode material.

13. The method of claim 10, wherein performing said at least one etching process on said layer of material through said etch mask results in the formation of a patterned layer of material comprised of a first plurality of layer features positioned above said first region of said semiconductor substrate and a second plurality of layer features positioned above said second region of said semiconductor substrate, wherein said first and second plurality of layer features have said same pitch spacing and wherein said first and second plurality of layer features have different widths.

14. The method of claim 13, further comprising:

removing said etch mask; and

performing an etching process on an underlying layer of material through said patterned layer of material.

15. The method of claim 9, wherein performing said first sidewall image transfer process to form said first plurality of spacers and said second plurality of spacers above said layer of material comprises:

forming a plurality of spaced-apart mandrel structures above said layer of material, wherein at least one of said mandrel structures is positioned above each of said first and second regions;

depositing a first layer of spacer material above said plurality of spaced-apart mandrel structures;

performing a first anisotropic etching process on said first layer of spacer material to define said first plurality of spacers and said second plurality of spacers; and

removing said plurality of spaced-apart mandrel structures.

16. The method of claim 15, wherein performing said second sidewall image transfer process comprises:

depositing a second layer of spacer material above said second plurality of spacers; and

performing a second anisotropic etching process on said second layer of spacer material to define said additional spacers.

17. A method, comprising:

forming a layer of material above a semiconductor substrate;

performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers above said layer of material, wherein said first plurality of spacers are positioned above a first region of said semiconductor substrate and said second plurality of spacers are positioned above a second region of said semiconductor substrate, wherein said first and second plurality of spacers have a same initial width and a same pitch spacing;

forming a masking layer that covers said first plurality of spacers but exposes said second plurality of spacers for further processing; and

performing an etching process on said exposed second plurality of spacers so as to result in a plurality of reduced-width spacers that have a width that is less than said initial width and wherein said first plurality of spacers and said plurality of reduced-width spacers define an etch mask.

18. The method of claim 17, further comprising:

removing said masking layer; and

performing at least one etching process on said layer of material through said etch mask.

19. The method of claim 17, wherein said layer of material is a layer of hard mask material.

20. The method of claim 17, wherein forming said layer of material comprises forming said layer of material above a layer of gate electrode material.

21. The method of claim 17, wherein performing said at least one etching process on said layer of material through said etch mask results in the formation of a patterned layer of material comprised of a first plurality of layer features positioned above said first region of said semiconductor substrate and a second plurality of layer features positioned above said second region of said semiconductor substrate, wherein said first and second plurality of layer features have said same pitch spacing and wherein said first and second plurality of layer features have different widths.

22. The method of claim 21, further comprising:

removing said etch mask; and

performing an etching process on an underlying layer of material through said patterned layer of material.

23. The method of claim 17, wherein performing said first sidewall image transfer process to form said first plurality of spacers and said second plurality of spacers above said layer of material comprises:

forming a plurality of spaced-apart mandrel structures above said layer of material, wherein at least one of said mandrel structures is positioned above each of said first and second regions;

depositing a first layer of spacer material above said plurality of spaced-apart mandrel structures;

performing a first anisotropic etching process on said first layer of spacer material to define said first plurality of spacers and said second plurality of spacers; and

removing said plurality of spaced-apart mandrel structures.