STACKED CARBON-BASED FETS
First Claim
Patent Images
1. A stacked transistor device, comprising:
- a lower channel layer formed on a substrate;
a pair of vertically aligned source regions formed directly over the lower channel layer, said pair of source regions being separated by an insulator;
a pair of vertically aligned drain regions formed directly over on the lower channel layer, said pair of drain regions being separated by an insulator;
a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and
an upper channel layer formed over the source regions, drain regions, and gate regions.
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Abstract
Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where the pair of drain regions are separated by an insulator; a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and an upper channel layer formed over the source regions, drain regions, and gate regions.
26 Citations
12 Claims
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1. A stacked transistor device, comprising:
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a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed directly over the lower channel layer, said pair of source regions being separated by an insulator; a pair of vertically aligned drain regions formed directly over on the lower channel layer, said pair of drain regions being separated by an insulator; a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and an upper channel layer formed over the source regions, drain regions, and gate regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification