Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle

• US 20140332899A1
• Filed: 07/28/2014
• Published: 11/13/2014
• Est. Priority Date: 08/05/2008
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 9,230,965 B2
• Time in Patent Office: Days
• US Class Current: 257/390
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state.

Claims

1-21. -21. (canceled)

22. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said semiconductor memory cells includes;

a floating body region configured to be charged to a level indicative of a state of the memory cell;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions;

a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and

a substrate region commonly connected to at least two of said memory cells, and when a first memory cell of said at least two of said memory cells is in a first state and a second memory cell of said at least two of said memory cells is in a second state, application of a bias via said substrate region maintains said first memory cell in said first state and said second memory cell in said second state.

23. The semiconductor memory array of claim 22, wherein said first region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said floating body region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;

said second region has said first conductivity type;

said buried layer region has said first conductivity type; and

said substrate region has said second conductivity type.

24. The semiconductor memory array of claim 22, wherein each of said memory cells further comprises insulating layers bounding side surfaces of said floating body region.

25. The semiconductor memory array of claim 22, wherein each of said memory cells further comprises:

a source line terminal electrically connected to one of said first and second regions;

a bit line terminal electrically connected to the other of said first and second regions;

a word line terminal connected to said gate;

a buried well terminal connected to said buried layer; and

a substrate terminal connected to said substrate region.

26. The semiconductor memory array of claim 22, wherein said substrate region is commonly connected to all of said memory cells in said memory array.

27. The semiconductor memory array of claim 22, wherein said substrate region is segmented to allow independent control of bias applied to a selected portion of said memory array.

28. The semiconductor memory array of claim 22, wherein said bias applied to said substrate region is a constant positive voltage bias.

29. The semiconductor memory array of claim 22, wherein said bias applied to said substrate region is a periodic pulse of positive voltage.

30. The semiconductor memory array of claim 22, wherein said floating body region and first and second regions are formed in a fin that extends above said buried layer, said gate is provided on opposite sides of said fin, between said first and second regions, and said floating body region is between said first and second regions.

31. The semiconductor memory array of claim 27, wherein said floating body region and said first and second regions are formed in a fin that extends above said buried layer, said gate is provided on opposite sides and adjacent to a top surface of said fin, between said first and second regions, and said floating body region is between said first and second regions.

32. A semiconductor memory cell comprising:

a silicon controlled rectifier device having a cathode region, a floating body region, a buried layer region, and an anode region, wherein;

a state of said memory cell is stored in said floating body region,

said buried layer region is located below said floating body region,

said anode region is located below said buried layer region, and

said state of said memory cell is maintained through a bias applied to said anode region.

33. The semiconductor memory cell of claim 32, wherein:

said floating base region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type,

said cathode region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type,

said buried layer region has said second conductivity type; and

said anode region has said first conductivity type.

34. The memory cell of claim 32, wherein said bias applied to said anode region is a constant positive voltage bias.

35. The memory cell of claim 32, wherein said bias applied to said anode region is a periodic pulse of positive voltage.

36. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said semiconductor memory cell includes;

a floating body region configured to be charged to a level indicative of a state of the memory cell;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions;

a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and

a substrate region positioned below said buried layer region;

wherein applying a voltage to said substrate region results in at least two stable floating body charge levels.

37. The semiconductor memory array of claim 36, wherein said voltage applied to said substrate region is a constant positive voltage bias.

38. The semiconductor memory array of claim 36, wherein said voltage applied to said substrate region is a periodic pulse of positive voltage.

39. The semiconductor memory array of claim 36, wherein said substrate region is commonly connected to all of said cells in said array.

40. The semiconductor memory array of claim 36, wherein said substrate region is segmented to allow independent control of bias applied on a selected portion of said memory array.