METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

• US 20140332942A1
• Filed: 04/23/2014
• Published: 11/13/2014
• Est. Priority Date: 05/10/2013
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: KANEMOTO, Koichi
• Granted Patent: US 9,275,945 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/4554 Coating
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/48479 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/78301 Capillary
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85203 : Thermocompression bonding
• CPC Class Codes: H01L 2224/85205 : Ultrasonic bonding
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/49 : wire-like arrangements or pins or rods using optical fibres H01L23/48; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/49503 : characterised by the die pad
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49551 : characterised by bent parts
• CPC Class Codes: H01L 23/49568 : specifically adapted to facilitate heat dissipation
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49582 : Metallic layers on lead frames
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of arranging a plurality of semiconductor chips next to each other over a chip mounting surface of a die pad. Further, the method of manufacturing a semiconductor device includes a step of electrically coupling the semiconductor chip and the semiconductor chip via a wire. In this regard, a pad (chip-to-chip connection pad) of the semiconductor chip on a second bonding side in the step of coupling the wire is provided such that it is distantly located from a peripheral portion of a surface of the semiconductor chip.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

(a) providing, respectively, a lead frame having a die pad, a plurality of suspension leads for supporting the die pad, and a plurality of leads arranged around the die pad in plan view,

a first semiconductor chip having a first main surface, a plurality of first pads formed over the first main surface and along each side of the first main surface, and a first back surface opposite to the first main surface, and

a second semiconductor chip having a second main surface, a plurality of second pads formed over the second main surface and along each side of the second main surface, and a second back surface opposite to the second main surface;

(b) after the step (a), mounting the first semiconductor chip over a first chip mounting region in a chip mounting surface of the die pad, and

mounting the second semiconductor chip over a second chip mounting region located next to the first chip mounting region in the chip mounting surface of the die pad;

(c) after the step (b), electrically coupling, respectively, a plurality of lead connection pads of the first pads of the first semiconductor chip with a first lead group of the leads via a plurality of first wires,

a plurality of lead connection pads of the second pads of the second semiconductor chip with a second lead group of the leads via a plurality of second wires, and

a plurality of chip-to-chip connection pads of the first pads of the first semiconductor chip with a plurality of chip-to-chip connection pads of the second pads of the second semiconductor chip via a plurality of third wires; and

(d) sealing the die pad, the first semiconductor chip, the second semiconductor chip, the first wires, the second wires and the third wires with resin such that a surface opposite to the chip mounting surface of the die pad and a part of each of the leads are exposed,

wherein, in the step (b), the first and second semiconductor chips are mounted such that a first side of the first main surface and a first side of the second main surface are next to each other;

wherein, in the step (c), after parts of the third wires are electrically coupled to the second semiconductor chip, the other parts of the third wires are electrically coupled to the first semiconductor chip, respectively;

wherein a distance between the first side of the first semiconductor chip and the chip-to-chip connection pads of the first semiconductor chip formed along the first side of the first semiconductor chip is greater than a distance between the first side of the semiconductor chip and the chip-to-chip connection pads of the second semiconductor chip formed along the first side of the second semiconductor chip, and

wherein, in a thickness direction of the lead frame, the first and second main surfaces of the first and second semiconductor chips are located between each of the leads and the die pad.

2. The method of manufacturing a semiconductor device according to claim 1,

wherein a thickness of the first semiconductor chip is smaller than a thickness of the second semiconductor chip.

3. The method of manufacturing a semiconductor device according to claim 2,

wherein a metal pattern is formed at a peripheral portion of the first main surface of the first semiconductor chip provided in the step (a).

4. The method of manufacturing a semiconductor device according to claim 3,

Wherein, in the step (d), with a state where parts of the first and semiconductor chips, the die pad, the first wires, the second wires, the third wires, and the leads are arranged, respectively, in a cavity of a molding die, a resin is supplied into the cavity in a pressed manner to form a sealing body.

5. The method of manufacturing a semiconductor device according to claim 1,

wherein, in the step (a), the first semiconductor chip over which a projecting element is formed in advance is provided over each of the chip-to-chip connection pads.

6. The method of manufacturing a semiconductor device according to claim 1,

wherein some of the lead connection pads of the first semiconductor chip are arranged along a second side of the first main surface of the first semiconductor chip provided in the step (a);

and

wherein a distance between the second side of the first semiconductor chip and the lead connection pads of the first semiconductor chip arranged along the second side of the first semiconductor chip is smaller than a distance between the first side of the first semiconductor chip and the chip-to-chip connection pads of the first semiconductor chip.

7. The method of manufacturing a semiconductor device according to claim 1,

wherein a first bent portion and a second bent portion are formed, respectively, at the suspension leads of the lead frame provided in the step (a).

8. The method of manufacturing a semiconductor device according to claim 1,

wherein a plurality of concave portions are formed around the first chip mounting region and the second chip mounting region in the die pad of the lead frame provided in the step (a).

9. The method of manufacturing a semiconductor device according to claim 3,

wherein a metal pattern is formed at a peripheral portion of the second main surface of the second semiconductor chip provided in the step (a).

10. A semiconductor device comprising:

a die pad;

a plurality of suspension leads coupled to the die pad;

a plurality of leads arranged around the die pad in plan view;

a first semiconductor chip having a first main surface, the first pads formed over the first main surface and along each side of the first main surface, and a first back surface opposite to the first main surface and mounted over a first chip mounting region in a chip mounting surface of the die pad;

a second semiconductor chip having a second main surface, the second pads formed over the second main surface and along each side of the second main surface, and a second back surface opposite to the second main surface and mounted over a second chip mounting region in the chip mounting surface of the die pad;

a plurality of first wires coupled to the lead connection pads of the first pads of the first semiconductor chip and to a first lead group of the leads;

a plurality of second wires coupled to the lead connection pads of the second pads of the second semiconductor chip and to a second lead group of the leads;

a plurality of third wires electrically coupled to chip-to-chip the connection pads of the first pads of the first semiconductor chip and to the chip-to-chip connection pads of the second pads of the second semiconductor chip; and

a sealing body for sealing the die pad, the first semiconductor chip, the second semiconductor chip, the first wires, the second wires, and the third wires such that part of a surface opposite to the chip mounting surface of the die pad and part of the leads are exposed, respectively,

wherein the first and second semiconductor chips are mounted over the die pad such that the first side of the first main surface and the first side of the second main surface are next to each other;

wherein a distance between the first side of the first semiconductor chip and the chip-to-chip connection pads of the first semiconductor chip formed along the first side of the first semiconductor chip is greater than a distance between the first side of the second semiconductor chip and the chip-to-chip connection pads of the second semiconductor chip formed along the first side of the second semiconductor chip, and

wherein the first and the second main surfaces of the first and the second semiconductor chips are located between the respective leads and the die pad in a thickness direction of the sealing body.

11. The semiconductor device according to claim 10,

wherein a thickness of the first semiconductor chip is smaller than a thickness of the second semiconductor chip.

12. The semiconductor device according to claim 11,

wherein a metal pattern is formed at a peripheral portion of the main surface of the first semiconductor chip.

13. The semiconductor device according to claim 10,

wherein a projecting electrode is formed over each of the chip-to-chip connection pads of the first semiconductor chip and one end of each of the third wires is joined to the projecting electrode.

14. The semiconductor device according to claim 10,

wherein some of the lead connection pads of the first semiconductor chip are arranged along the second side of the first main surface of the first semiconductor chip, and

wherein a distance between the second side of the first semiconductor chip and the lead connection pads of the first semiconductor chip arranged along the second side of the first semiconductor chip is smaller than a distance between the first side of the first semiconductor chip and the chip-to-chip connection pads of the first semiconductor chip.

15. The semiconductor device according to claim 10,

wherein a first bent portion and a second bent portion are formed at each of the suspension leads.

16. The semiconductor device according to claim 10,

wherein a plurality of concave portions are formed around the first chip mounting region and the second chip mounting region of the die pad.

17. The semiconductor device according to claim 12,

wherein a metal pattern is formed at a peripheral portion of the second surface of the second semiconductor chip.