CIRCUIT DEVICE

• US 20140333149A1
• Filed: 07/23/2014
• Published: 11/13/2014
• Est. Priority Date: 07/03/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kawano, Masaya, Nakashiba, Yasutaka
• Granted Patent: US 9,502,175 B2
• Time in Patent Office: Days
• US Class Current: 307/104
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0073 with a special conductive pattern, e.g. flat spiral
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate inductors for integrated circuits H01L28/10
• CPC Class Codes: H01F 2027/2809 on stacked layers
• CPC Class Codes: H01F 2038/143 for signals
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 38/14 Inductive couplings for wireless supply or distribution of electric power using inductive coupling H02J50/10
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/30107 Inductance

Abstract

A circuit device includes a semiconductor substrate, a first inductor provided over the semiconductor substrate, and a second inductor provided over the semiconductor substrate and coupled to the first inductor. The first inductor and second inductor are wound in a same direction with each other from respective inner end portions to respective outer end portions thereof.

Claims

1. A circuit device, comprising:

a semiconductor substrate;

a first inductor provided over said semiconductor substrate; and

a second inductor provided over said semiconductor substrate and coupled to said first inductor,

wherein said first inductor and said second inductor are wound in a same direction with each other from respective inner end portions to respective outer end portions thereof.

2. The circuit device according to claim 1, further comprising:

a third inductor provided over said semiconductor substrate and located in a region overlapping with said first inductor when viewed from a direction perpendicular to said semiconductor substrate, said third inductor being positioned at a region between said semiconductor substrate and said first inductor; and

a fourth inductor provided over said semiconductor substrate and overlapping with said second inductor when viewed from a direction perpendicular to said semiconductor substrate, said fourth inductor being positioned at a region between said semiconductor substrate and said second inductor.

3. The circuit device according to claim 1, wherein said respective outer end portions a are coupled to each other.

4. The circuit device according to claim 1, wherein said respective inner end portions are coupled to each other.

5. The circuit device according to claim 2, further comprising:

a first interconnect provided over said semiconductor substrate and coupled to said third inductor; and

a second interconnect provided over said semiconductor substrate and coupled to said fourth inductor.