METHOD AND DEVICES FOR NON-INTRUSIVE POWER MONITORING

• US 20140333281A1
• Filed: 05/09/2013
• Published: 11/13/2014
• Est. Priority Date: 05/09/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: LI, Qing
• Granted Patent: US 9,400,295 B2
• Time in Patent Office: Days
• US Class Current: 323/318
• CPC Class Codes: G01R 21/00 Arrangements for measuring electric power or power factor G01R7/12 takes precedence
• CPC Class Codes: G05F 5/00 Systems for regulating electric variables by detecting deviations in the electric input to the system and thereby controlling a device within the system to obtain a regulated output
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 1/0019 the disturbance parameters being load current fluctuations
• CPC Class Codes: H02M 1/15 using active elements
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and device are disclosed for estimating a power demand level of an active circuit on a power supply line. A ripple amplitude and a ripple frequency associated with operation of the active circuit may be monitored on the power supply line. The ripple amplitude and ripple frequency may be compared with corresponding references. The ripple amplitude and ripple frequency may be associated with an estimated power demand level of the active circuit on the power supply line based on the comparison. A ripple generator generates a controlled ripple on the power supply line for calibration.

Claims

1. A method of estimating a power demand level of an active circuit, comprising:

measuring a ripple amplitude and a ripple frequency on a power supply line coupled to the active circuit;

converting the ripple amplitude and the ripple frequency into a ripple amplitude index and a ripple frequency index; and

using the ripple amplitude index and the ripple frequency index to obtain an estimated power demand level of the active circuit.

2. The method according to claim 1, wherein using the ripple amplitude index and the ripple frequency index to obtain an estimated power demand level of the active circuit comprises using the ripple amplitude index and the ripple frequency index to look up a stored value for the estimated power demand level.

3. The method according to claim 1, wherein using the ripple amplitude index and the ripple frequency index to obtain an estimated power demand level of the active circuit comprises using the ripple amplitude index and the ripple frequency index in a table lookup operation to obtain the estimated power demand level from a datatable of estimated power demand levels indexed to ripple amplitude index and ripple frequency index values.

4. The method according to claim 3, wherein estimated power demand levels stored in the datatable of estimated power demand levels are calculated based on an intrinsic inductance of the power supply line and an intrinsic capacitance of the active circuit established during a calibration procedure.

5. The method according to claim 1, further comprising using the estimated power demand level of the active circuit to control a level of the power supply line.

6. The method according to claim 1, further comprising using the estimated power demand level of the active circuit to identify a peak power usage condition and to control a level of the power supply line in response to identifying the peak power usage condition before a critical thermal level is reached.

7. The method according to claim 1, wherein:

the power supply line is associated with a digital circuit; and

measuring a ripple amplitude and a ripple frequency on a power supply line coupled to the active circuit comprises non-intrusively measuring the ripple amplitude and the ripple frequency using an analog circuit with a high input impedance coupled to the power supply line.

8. The method according to claim 1, wherein the active circuit includes a system-on-chip (SoC) circuit.

9. A method of calibrating a power monitor circuit for estimating a power demand level of an active circuit on a power supply line, the method comprising:

disabling a clock associated with the active circuit;

inputting a first switching signal into a calibrated test load coupled to the power supply line, the calibrated test load having a known value, the first switching signal having a first lower frequency less than an intrinsic frequency of the active circuit;

using the power monitor circuit to measure a ripple amplitude and a ripple frequency on the power supply line associated with inputting the first switching signal; and

calculating an intrinsic capacitance of the active circuit and an intrinsic inductance of the power supply line based on the ripple amplitude and the ripple frequency.

10. The method according the claim 9, further comprising determining a leakage current associated with the active circuit using the calibrated test load, the intrinsic capacitance and the intrinsic inductance.

11. The method according to claim 10, further comprising:

inputting a second switching signal into the test load, the second switching signal having a second lower frequency than the first switching signal;

measuring a line current in the power supply line; and

calibrating the test load and establishing the known value of the calibrated test load using the intrinsic capacitance, the intrinsic inductance, the measured line current and the determined leakage current.

12. The method according to claim 9, further comprising:

inputting a plurality of switching signals each having representative amplitudes and representative frequencies into the calibrated test load;

determining an estimated power demand level of the active circuit on the power supply line for each combination of the representative amplitudes and frequencies of the plurality of switching signals; and

storing in a memory the estimated power demand level for each combination of the representative amplitudes and frequencies of the plurality of switching signals.

13. The method according to claim 12, wherein storing in a memory the estimated power demand level for each combination of the representative amplitudes and frequencies of the plurality of switching signals comprises storing the estimated power demand level for each combination in a lookup table in which each estimated power demand levels is indexed to a particular combination of representative amplitudes and frequencies.

14. A power monitor circuit configured to estimate a power demand level of an active circuit on a power supply line, the power monitor circuit comprising:

an interface having leads configured to non-intrusively couple the power monitor circuit to a power supply line of the active circuit;

a measurement circuit coupled to the interface, the measurement circuit comprising;

a ripple amplitude measurement section configured to measure a ripple amplitude of the power supply line when the leads are coupled to the power supply line; and

a ripple frequency measurement section configured to measure a ripple frequency of the power supply line when the leads are coupled to the power supply line;

a conversion circuit coupled to the measurement circuit, the conversion circuit comprising;

a ripple amplitude conversion section configured to convert the ripple amplitude into a ripple amplitude index; and

a ripple frequency conversion section configured to convert the ripple frequency into a ripple frequency index; and

a memory coupled to the interface the measurement circuit and the conversion circuit, the memory storing a plurality of estimated power demand levels indexed to ripple amplitude indices and ripple frequency indices.

15. The power monitor circuit according to claim 14, an output circuit coupled to the memory and the conversion circuit and configured to use the ripple amplitude index and the ripple frequency index to obtain and output a corresponding estimate of power demand level from the memory.

16. The power monitor circuit according to claim 14, wherein the measurement circuit comprises an analog circuit having a high input impedance that is non-intrusively coupled to the interface.

17. The power monitor circuit according to claim 14, wherein the active circuit comprises a system-on-chip (SoC) circuit.

18. The power monitor circuit according to claim 14, wherein the memory stores the plurality of estimated power demand levels indexed to ripple amplitude indices and ripple frequency indices in a lookup table.

19. The power monitoring circuit according to claim 14, further comprising a calibration circuit comprising:

a calibrated test load having a known resistance value; and

a switch coupled configured to connect the calibrated test load to the interface,

wherein the calibration circuit is configured to control the switch to generate a first calibration signal on the power supply line through the calibrated test load when the leads are coupled to the power supply line, the first calibration signal having first frequency lower than an intrinsic frequency of the active circuit when a clock associated with operation of the active circuit is disabled, and

wherein the power monitoring circuit is further configured to;

measure a ripple amplitude and a ripple frequency associated with the first calibration signal through the calibrated test load; and

calculate an intrinsic capacitance of the active circuit and an intrinsic inductance of the power supply line based on the ripple amplitude and the ripple frequency.

20. The power monitoring circuit according to claim 19, wherein the monitoring circuit is further configured to determine a leakage current associated with the active circuit using the calibrated test load, the calculated intrinsic capacitance, and the calculated intrinsic inductance.

21. The power monitoring circuit according to claim 20, wherein:

the calibration circuit is further configured to control the switch to generate a second calibration signal on the power supply line through the calibrated test load, the second calibration signal having a second frequency lower than the first frequency when the clock associated with the operation of the active circuit is disabled; and

the monitoring circuit is further configured to;

measure a line current in the power supply line; and

calibrate the test load and establish the known value of the calibrated test load using the intrinsic capacitance, the calculated intrinsic inductance, the measured line current and the determined leakage current.

22. The power monitoring circuit according to claim 21, wherein:

the calibration circuit is further configured to control the switch to generate a plurality of ripple calibration signals on the power supply line through the calibrated test load, each of the plurality of ripple calibration signals having a representative amplitude and representative frequency; and

the monitoring circuit is further configured to provide an estimated power demand level of the active circuit on the power supply line for each combination of the representative amplitudes and representative frequencies of the plurality of ripple calibration signals.

23. A power monitor circuit, comprising:

means for measuring a ripple amplitude and a ripple frequency on a power supply line coupled to an active circuit;

means for converting the ripple amplitude and the ripple frequency into a ripple amplitude index and a ripple frequency index; and

means for using the ripple amplitude index and the ripple frequency index to obtain an estimated power demand level of the active circuit.

24. The power monitor circuit according to claim 23, wherein means for using the ripple amplitude index and the ripple frequency index to obtain an estimated power demand level of the active circuit comprises means for using the ripple amplitude index and the ripple frequency index to look up a stored value for the estimated power demand level.

25. The power monitor circuit according to claim 23, wherein means for using the ripple amplitude index and the ripple frequency index to obtain an estimated power demand level of the active circuit comprises means for using the ripple amplitude index and the ripple frequency index in a table lookup operation to obtain the estimated power demand level from a datatable of estimated power demand levels indexed to ripple amplitude index and ripple frequency index values.

26. The power monitor circuit according to claim 25, wherein estimated power demand levels stored in the datatable of estimated power demand levels are calculated based on an intrinsic inductance of the power supply line and an intrinsic capacitance of the active circuit established during a calibration procedure.

27. The power monitor circuit according to claim 23, further comprising means for using the estimated power demand level of the active circuit to control a level of the power supply line.

28. The power monitor circuit according to claim 23, wherein:

the power supply line is associated with a digital circuit; and

means for measuring a ripple amplitude and a ripple frequency on a power supply line coupled to the active circuit comprises means for non-intrusively measuring the ripple amplitude and the ripple frequency using an analog circuit with a high input impedance coupled to the power supply line.

29. The power monitor circuit according to claim 23, wherein the active circuit includes a system-on-chip (SoC) circuit.

30. The power monitor circuit according to claim 23, further comprising:

means for disabling a clock associated with the active circuit;

means for inputting a first switching signal into a calibrated test load coupled to the power supply line, the calibrated test load having a known value, the first switching signal having a first lower frequency less than an intrinsic frequency of the active circuit;

means for using the power monitor circuit to measure a ripple amplitude and a ripple frequency on the power supply line associated with inputting the first switching signal; and

means for calculating an intrinsic capacitance of the active circuit and an intrinsic inductance of the power supply line based on the ripple amplitude and the ripple frequency.

31. The power monitor circuit according the claim 30, further comprising means for determining a leakage current associated with the active circuit using the calibrated test load, the calculated intrinsic capacitance, and the calculated intrinsic inductance.

32. The power monitor circuit according to claim 31, further comprising:

means for inputting a second switching signal into the calibrated test load, the second switching signal having a second lower frequency than the first switching signal;

means for measuring a line current in the power supply line; and

means for calibrating the test load and establishing the known value using the intrinsic capacitance, the intrinsic inductance, the measured line current and the determined leakage current.

33. The power monitor circuit according to claim 30, further comprising:

means for inputting a plurality of switching signals each having representative amplitudes and representative frequencies into the calibrated test load;

means for determining an estimated power demand level of the active circuit on the power supply line for each combination of the representative amplitudes and frequencies of the plurality of switching signals; and

means for storing the estimated power demand level for each combination of the representative amplitudes and frequencies of the plurality of switching signals.

34. The power monitor circuit according to claim 33, wherein means for storing the estimated power demand level for each combination of the representative amplitudes and frequencies of the plurality of switching signals comprises means for storing the estimated power demand level for each combination in a lookup table in which each estimated power demand levels is indexed to a particular combination of representative amplitudes and frequencies.