METHOD AND SYSTEM FOR PROVIDING AUTOMATIC GATE BIAS AND BIAS SEQUENCING FOR FIELD EFFECT TRANSISTORS

• US 20140333382A1
• Filed: 01/07/2014
• Published: 11/13/2014
• Est. Priority Date: 03/25/2010
• Status: Active Grant

• Current Assignee: Emhiser Research Inc
• Original Assignee: Emhiser Research Inc
• Inventors: Lautzenhiser, Llyod L.
• Granted Patent: US 8,963,643 B2
• Time in Patent Office: Days
• US Class Current: 330/285
• CPC Class Codes: H03F 1/0216 Continuous control
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/129 there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/15 the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/24 the supply or bias voltage or current at the source side of a FET being continuously controlled by a controlling signal
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/462 the current being sensed
• CPC Class Codes: H03F 3/16 with field-effect devices
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence

Abstract

A feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of LDFET, GaNFET, GaAsFET, and JFET type transistors used in such circuits. A transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations. Additional circuits to provide temperature compensation, RF power monitoring and drain current control, RF output power leveler, high power gain block, and optional digital control of various functions. A gate bias circuit including a bias sequencer and negative voltage deriver for operation of N-channel depletion mode devices.

Claims

1. An RF amplifier circuit comprising:

FET for receiving a RF input signal and generating an amplified RF output signal, the FET having a gate, drain, and source;

control circuit, connected to the gate and drain of the FET, for controlling the current at the drain;

dividing circuit comprising a means for biasing and variably compensating drift in the gate threshold voltage required to set the quiescent drain current, the dividing circuit being connected to the control circuit and controlling operation of the control circuit to maintain an essentially constant current at the drain in connection with a wake-up transition;

detecting means, operably connected to the RF output signal, for detecting the power level of the RF output signal and supplying a DC voltage representative of the detected output power level;

means for producing a variable reference voltage; and

adjusting means, connected to the detecting means, the variable reference voltage and the dividing circuit, for automatically adjusting the drain current based at least in part on a comparison of the supplied DC voltage and the reference voltage by an amount necessary to maintain essentially constant output RF power.

2. The circuit of claim 1, further comprising a small value capacitor, operably connected to the RF output signal and the detecting means.

3. The circuit of claim 1, wherein the reference voltage is a digital computer-controlled reference voltage input, and further comprising a digital-to-analog convertor operably connected to the digital input and the adjusting means and adapted to supply a computer-controllable analog reference voltage signal to the adjusting means.