APPARATUS FOR DISTRIBUTING BUS TRAFFIC OF MULTIPLE CAMERA INPUTS OF AUTOMOTIVE SYSTEM ON CHIP AND AUTOMOTIVE SYSTEM ON CHIP USING THE SAME
First Claim
1. An apparatus for distributing bus traffic of multiple camera inputs of an automotive system on chip (SoC), the apparatus comprising:
- a plurality of camera data caches configured to store data from the plurality of cameras in corresponding internal buffers, to measure data storage status of the buffers, and to transmit the data to memory based on obtained right to use a bus;
a bus monitor configured to analyze a bus signal, and to then output a signal capable of allowing the plurality of camera data caches to transmit the data via the bus based on results of the analysis; and
a master arbiter configured to, in response to reception of the signal capable of allowing transmission of the data, determine priorities of use of the bus of the plurality of camera data caches, and provide a right to use the bus to the plurality of camera data caches based on the priorities of use of the bus.
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Abstract
An apparatus for distributing the bus traffic of the multiple camera inputs of an automotive system on chip (SoC) and an automotive SoC using the apparatus are disclosed. The plurality of camera data caches stores data from the plurality of cameras in corresponding internal buffers, measures the data storage status of the buffers, and transmits the data to memory. The bus monitor analyzes a bus signal, and then outputs a signal capable of allowing the plurality of camera data caches to transmit the data via the bus based on the results of the analysis. The master arbiter determines the priorities of use of the bus of the camera data caches, and provides the right to use the bus to the plurality of camera data caches based on the priorities of use of the bus.
21 Citations
10 Claims
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1. An apparatus for distributing bus traffic of multiple camera inputs of an automotive system on chip (SoC), the apparatus comprising:
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a plurality of camera data caches configured to store data from the plurality of cameras in corresponding internal buffers, to measure data storage status of the buffers, and to transmit the data to memory based on obtained right to use a bus; a bus monitor configured to analyze a bus signal, and to then output a signal capable of allowing the plurality of camera data caches to transmit the data via the bus based on results of the analysis; and a master arbiter configured to, in response to reception of the signal capable of allowing transmission of the data, determine priorities of use of the bus of the plurality of camera data caches, and provide a right to use the bus to the plurality of camera data caches based on the priorities of use of the bus. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An automotive SoC, comprising:
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a plurality of camera data caches configured to store data from the plurality of cameras in corresponding internal buffers, to measure data storage status of the buffers, and to transmit the data to memory based on obtained right to use a bus; a bus monitor configured to analyze a bus signal, and to then output a signal capable of allowing the plurality of camera data caches to transmit the data via the bus based on results of the analysis; a master arbiter configured to, in response to reception of the signal capable of allowing transmission of the data, determine priorities of use of the bus of the plurality of camera data caches, and provide a right to use the bus to the plurality of camera data caches based on the priorities of use of the bus; and a processor configured to execute a program stored in memory. - View Dependent Claims (9, 10)
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Specification