Merging Result from a Parser in a Network Processor with Result from an External Coprocessor

• US 20140337677A1
• Filed: 05/10/2013
• Published: 11/13/2014
• Est. Priority Date: 02/07/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Basso, Claude, Calvignac, Jean L., Chang, Chih-jen, Damon, Philippe, Vaidhyanathan, Natarajan, Verplanken, Fabrice J., Verrilli, Colin B.
• Granted Patent: US 8,949,856 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues

Abstract

A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.

Claims

1. A method for managing in a network processor results from a parser analyzing an incoming data packet, the method comprising:

enqueueing in a result queue a parser result coming from the parser, wherein the parser result indicates whether the parser result is complete or needs to be completed by a coprocessor result;

enqueuing in an additional queue an entry containing an address of the entry in the result queue and the indication that the parser result is complete or needs to be completed;

determining whether a first entry in the additional queue refers to a parser result to be completed; and

responsive to determining the first entry in the additional queue refers to a parser result to be completed, responsive to receiving a coprocessor result in a response register, merging the coprocessor result from the response register with a parser result read from the result queue using the address from the first entry in the additional queue to form a completed result, writing the completed result in the result queue, and exposing the completed result to a dequeue and sequential sending process for further processing by the network processor.

3. The method of claim 1 further comprising:

testing whether a cyclical redundancy check (CRC) included in the coprocessor result is valid; and

responsive to the CRC not being valid, indicating in the corresponding entry in the result queue for upper layers of the network processor to discard the result.

4. The method of claim 3 wherein the indicating in the corresponding entry in the result queue for upper layers of the network processor to discard the result comprises setting a discard bit of the entry.

5. The method of claim 1, further comprising:

adding to the additional queue entry a sequence number;

determining whether a response sequence number included in the coprocessor response is identical to a sequence number stored in the first entry of the additional queue; and

responsive to determining the response sequence number is not identical to the sequence number stored in the first entry of the additional queue, indicating in the corresponding entry in the result FIFO queue for the upper layers of the network processor to discard the result.

6. The method of claim 5 wherein indicating in the result queue entry for the upper layers of the network processor to discard the result comprises setting a discard bit of the entry.

7. The method of any one of claim 1, wherein merging the coprocessor result with the parser result comprises reading in the coprocessor response a configuration to be applied to the merge operation and applying the configuration to multiplexors forming a bit-wise multiplex implemented merging logic.

2. (canceled)

8. (canceled)

9. (canceled)

10. A network processor comprising:

a processor bus;

at least one processor connected to the processor bus; and

a network adapter connected to the processor bus and an external coprocessor, wherein the network adapter comprises a result queue, an additional queue, a response register, a parser, and result queue management logic,

wherein the result queue management logic enqueues in the result queue a parser result coming from the parser, wherein the parser result indicates whether the parser result is complete or needs to be completed by a coprocessor result from the external coprocessor;

wherein result queue management logic enqueues in the additional queue an entry containing an address of the entry in the result queue and the indication that the parser result is complete or needs to be completed;

wherein the result queue management logic determines whether a first entry in the additional queue refers to a parser result to be completed; and

wherein responsive to determining the first entry in the additional queue refers to a parser result to be completed and responsive to receiving a coprocessor result in a response register, the result queue management logic merges the coprocessor result from the response register with a parser result read from the result queue using the address from the first entry in the additional queue to form a completed result, writes the completed result in the result queue, and exposes the completed result to a dequeue and sequential sending process for further processing by the network processor.

11. The network processor of claim 10, wherein the result queue management logic tests whether a cyclical redundancy check (CRC) included in the coprocessor result is valid;

and

wherein responsive to the CRC not being valid, the result queue management logic indicates in the corresponding entry in the result queue for upper layers of the network processor to discard the result.

12. The network processor of claim 11 wherein the indicating in the corresponding entry in the result queue for upper Layers of the network processor to discard the result comprises setting a discard bit of the entry.

13. The network processor of claim 10, wherein the network adapter adds to the additional queue entry a sequence number;

wherein the result queue management logic determines whether a response sequence number included in the coprocessor response is identical to a sequence number stored in the first entry of the additional queue; and

wherein responsive to determining the response sequence number is not identical to the sequence number stored in the first entry of the additional queue, the result queue management logic indicates in the corresponding entry in the result queue for the upper layers of the network processor to discard the result.

14. The network processor of claim 13, wherein indicating in the result queue entry for the upper layers of the network processor to discard the result comprises setting a discard bit of the entry.

15. The network processor of claim 10, wherein merging the coprocessor result with the parser result comprises reading in the coprocessor response a configuration to be applied to the merge operation and applying the configuration to multiplexors forming a bit-wise multiplex implemented merging logic.

16. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a network adapter in a network processor, causes the network adapter to:

enqueue in a result queue a parser result coming from a parser, wherein the parser result indicates whether the parser result is complete or needs to be completed by a coprocessor result from the external coprocessor;

enqueue in an additional queue an entry containing an address of the entry in result queue and the indication that the parser result is complete or needs to be completed;

determine whether a first entry in the additional queue refers to a parser esult to be completed; and

responsive to determining the first entry in the additional queue refers to a parser result to be completed and responsive to receiving a coprocessor result in a response register, merge the coprocessor result from the response register with a parser result read from the result queue using the address from the first entry in the additional queue to form a completed result, write the completed result in the result queue, and expose the completed result to a dequeue and sequential sending process for further processing by the network processor.

17. The computer program product of claim 16, wherein the computer readable program further causes the network adapter to:

test whether a cyclical redundancy check (CRC) included in the coprocessor result is valid; and

responsive to the CRC not being valid, indicate in the corresponding entry in the result queue for upper layers of the network processor to discard the result.

18. The computer program product of claim 17, wherein indicating in the corresponding entry in the result queue for upper layers of the network processor to discard the result comprises setting a discard bit of the entry.

19. The computer program product of claim 16, wherein the computer readable program further causes the network adapter to:

add to the additional queue entry a sequence number;

determine whether a response sequence number included in the coprocessor response is identical to a sequence number stored in the first entry of the additional queue; and

responsive to determining the response sequence number is not identical to the sequence number stored in the first entry of the additional queue, indicate in the corresponding entry in the result queue for the upper layers of the network processor to discard the result.

20. The computer program product of claim 19, wherein indicating in the result queue entry for the upper layers of the network processor to discard the result comprises setting a discard bit of the entry.

21. The computer program product of claim 16, wherein merging the coprocessor result with the parser result comprises reading in the coprocessor response a configuration to be applied to the merge operation and applying the configuration to multiplexors forming a bit-wise multiplex implemented merging logic.