Vertical Light Emitting Diode (VLED) Dice Having Confinement Layers With Roughened Surfaces And Methods Of Fabrication

• US 20140339496A1
• Filed: 05/16/2013
• Published: 11/20/2014
• Est. Priority Date: 01/11/2005
• Status: Active Grant

• Current Assignee: Semileds Optoelectronics Company Limited (SemiLEDs Inc)
• Original Assignee: Chen-Fu Chu
• Inventors: Cheng, Hao-Chun, Liu, Wen-Huang, Cheng, Chao-Chen, Chu, Chen-FU, Fan, Feng-Hsu, Doan, David Trung, Wen, Yang Po
• Granted Patent: US 9,130,114 B2
• Time in Patent Office: Days
• US Class Current: 257/13
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/04 with a quantum effect structure or superlattice, e.g. tunnel junction
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers

Abstract

A vertical light emitting diode (VLED) die includes an epitaxial structure having a first-type confinement layer, an active layer on the first-type confinement layer configured as a multiple quantum well (MQW) configured to emit light, and a second-type confinement layer having a roughened surface. In a first embodiment, the roughened surface includes a pattern of holes with a depth (d) in a major surface thereof surrounded by a pattern of protuberances with a height (h) on the major surface. In a second embodiment, the roughened surface includes a pattern of primary protuberances surrounded by a pattern of secondary protuberances.

Claims

1. A vertical light emitting diode (VLED) die comprising:

a first-type confinement layer;

an active layer on the first-type confinement layer comprising a multiple quantum well (MQW) configured to emit light; and

a second-type confinement layer comprising a roughened surface having a major surface with a pattern of holes therein with a depth (d) in the major surface surrounded by a pattern of protuberances with a height (h) on the major surface.

2. The vertical light emitting diode (VLED) die of claim 1 wherein the holes include smooth sidewalls and a bottom surface having a pattern of second protuberances.

3. The vertical light emitting diode (VLED) die of claim 1 wherein the holes have a generally hexagonal peripheral shape.

4. The vertical light emitting diode (VLED) die of claim 1 wherein the holes have a shape selected from the group consisting of circular, square, rectangular, oval and polygonal.

5. The vertical light emitting diode (VLED) die of claim 1 wherein the protuberances have a generally pyramidal, truncated pyramidal or ziggurat shape.

6. The vertical light emitting diode (VLED) die of claim 1 wherein the protuberances have sidewalls at an angle greater than 90°

with respect to the major surface.

7. The vertical light emitting diode (VLED) die of claim 1 wherein the pattern of protuberances includes a plurality of primary protuberances surrounded by a pattern of secondary protuberances.

8. The vertical light emitting diode (VLED) die of claim 1 wherein the first-type confinement layer comprises a p-type semiconductor layer and the second-type confinement layer comprises an n-type semiconductor layer.

9. A vertical light emitting diode (VLED) die comprising:

a first-type confinement layer;

an active layer on the first-type confinement layer comprising a multiple quantum well (MQW) configured to emit light; and

a second-type confinement layer comprising a roughened surface having a major surface with a pattern of primary protuberances surrounded by a pattern of secondary protuberances, whit the primary protuberances having a larger size and a larger height on the major surface than the secondary protuberances.

10. The vertical light emitting diode (VLED) die of claim 9 wherein the primary protuberances have a generally pyramidal, truncated pyramidal or ziggurat shape.

11. The vertical light emitting diode (VLED) die of claim 9 wherein the secondary protuberances have a generally pyramidal, truncated pyramidal or ziggurat shape.

12. The vertical light emitting diode (VLED) die of claim 9 wherein the primary protuberances have sidewalls at an angle greater than 90°

with respect to the major surface.

13. The vertical light emitting diode (VLED) die of claim 9 wherein the secondary protuberances have sidewalls at an angle greater than 90°

with respect to the major surface,

14. The vertical light emitting diode (VLED) die of claim 9 wherein the first-type confinement layer comprises a p-type semiconductor layer and the second-type confinement layer comprises an n-type semiconductor layer.

15. A method for fabricating vertical light emitting diode (VLED) dice comprising:

providing a carrier substrate;

forming a first-type confinement layer on the carrier substrate;

forming an active layer on the first-type confinement layer;

forming a second-type confinement layer;

removing the carrier substrate; and

roughening an outer surface of the second-type confinement layer to form a roughened surface having a major surface with a pattern of holes therein with a depth (d) in the major surface surrounded by a pattern of protuberances with a height (h) on the major surface.

16. The method of claim 15 wherein the holes include smooth sidewalls and a bottom surface having a pattern of second protuberances.

17. The method of claim 15 wherein the holes have a generally hexagonal peripheral shape.

18. The method of claim 15 wherein the protuberances have a generally pyramidal, truncated pyramidal or ziggurat shape.

19. The method of claim 15 wherein the protuberances have sidewalls at an angle greater than 90°

with respect to the major surface.

20. The method of claim 15 wherein the pattern of protuberances includes a plurality of primary protuberances surrounded by a pattern of secondary protuberances.

21. The method of claim 15 wherein the first-type confinement layer comprises a p-type semiconductor layer and the second-type confinement layer comprises an n-type semiconductor layer.