METHODS OF FORMING SEMICONDUCTOR DEVICES WITH DIFFERENT INSULATION THICKNESSES ON THE SAME SEMICONDUCTOR SUBSTRATE AND THE RESULTING DEVICES

• US 20140339645A1
• Filed: 05/14/2013
• Published: 11/20/2014
• Est. Priority Date: 05/14/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Lian, Jun
• Granted Patent: US 8,877,625 B1
• Time in Patent Office: Days
• US Class Current: 257/392
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

One method includes forming first and second devices by forming a first layer of gate insulation material having a first thickness for the first device, forming a layer of high-k insulation material having a second thickness that is less than the first thickness for the second device and forming first and second metal-containing gate electrode structures that contact the first layer of gate insulation material and the high-k insulation material. A device disclosed herein includes first and second semiconductor devices wherein the first gate structure comprises a layer of insulating material having a first portion of a first metal layer positioned on and in contact with the layer of insulating material and a second gate structure comprised of a layer of high-k insulation material and a second portion of the first metal layer positioned on and in contact with the layer of high-k insulation material.

Claims

1. A method of forming first and second semiconductor devices above a common semiconductor substrate, comprising:

forming a first layer of gate insulation material above said substrate at least at a location where a channel region of said first semiconductor device will be formed, wherein said first layer of gate insulation material is formed to a first substantially uniform thickness;

forming a first patterned mask layer that covers said first semiconductor device but exposes said second semiconductor device for further processing;

with said patterned mask layer in position, forming a layer of high-k insulation material above said substrate where a channel region of said second semiconductor device will be formed, wherein said layer of high-k insulation material is formed to a second substantially uniform thickness that is less than said substantially uniform first thickness of said first layer of gate insulation material;

removing said patterned mask layer; and

performing at least one common process operation to form a first metal-containing gate electrode structure for said first semiconductor device and a second metal-containing gate electrode structure for said second semiconductor device, wherein a portion of said first metal-containing gate electrode structure is formed on and in contact with said first layer of gate insulation material and a portion of said second metal-containing gate electrode structure is formed on and in contact with said high-k insulation material.

2. The method of claim 1, wherein performing said at least one common process operation to form a first metal-containing gate electrode structure for said first semiconductor device and a second metal-containing gate electrode structure for said second semiconductor device comprises performing a common metal deposition process to form a work function adjusting metal layer on and in contact with said first layer of gate insulation material and on and in contact with said high-k insulation material.

3. The method of claim 2, further comprising performing at least one additional metal deposition process to form at least one additional layer of metal on said work function adjusting metal layer.

4. The method of claim 1, wherein performing said at least one common process operation to form a first metal-containing gate electrode structure for said first semiconductor device and a second metal-containing gate electrode structure for said second semiconductor device comprises:

performing a plurality of metal deposition processes to form a plurality of metal layers, wherein one of said plurality of metal layers is formed on and in contact with said first layer of gate insulation material and on and in contact with said high-k insulation material; and

performing at least one chemical mechanical planarization process.

5. The method of claim 1, wherein said first layer of gate insulation material is comprised of a layer of silicon dioxide.

6. The method of claim 1, wherein said first and second devices are one of planar field-effect transistors or FinFET transistors.

7. A method of forming first and second semiconductor devices above a common semiconductor substrate, comprising:

forming a first layer of gate insulation material above said substrate at least at locations where channel regions of said first and second semiconductor devices will be formed, wherein said first layer of gate insulation material is formed to a first substantially uniform thickness;

forming a first patterned mask layer that covers said first semiconductor device but exposes said second semiconductor device for further processing;

with said patterned mask layer in position;

removing a portion of said first layer of gate insulation material from above a location where said second channel region will be formed so as to thereby expose a portion of said substrate; and

forming a layer of high-k insulation material above said exposed portion of said substrate, wherein said layer of high-k insulation material is formed to a second substantially uniform thickness that is less than said first uniform thickness of said first layer of gate insulation material;

removing said patterned mask layer; and

performing at least one common process operation to form a first metal-containing gate electrode structure for said first semiconductor device and a second metal-containing gate electrode structure for said second semiconductor device, wherein a portion of said first metal-containing gate electrode structure is formed on and in contact with said first layer of gate insulation material and a portion of said second metal-containing gate electrode structure is formed on and in contact with said high-k insulation material.

8. The method of claim 7, wherein performing said at least one common process operation to form a first metal-containing gate electrode structure for said first semiconductor device and a second metal-containing gate electrode structure for said second semiconductor device comprises performing a common metal deposition process to form a work function adjusting metal layer on and in contact with said first layer of gate insulation material and on and in contact with said high-k insulation material.

9. The method of claim 8, further comprising performing at least one additional metal deposition process to form at least one additional layer of metal on said work function adjusting metal layer.

10. The method of claim 7, wherein performing said at least one common process operation to form a first metal-containing gate electrode structure for said first semiconductor device and a second metal-containing gate electrode structure for said second semiconductor device comprises:

performing a plurality of metal deposition processes to form a plurality of metal layers, wherein one of said plurality of metal layers is formed on and in contact with said first layer of gate insulation material and on and in contact with said high-k insulation material; and

performing at least one chemical mechanical planarization process.

11. The method of claim 7, wherein said first layer of gate insulation material is comprised of a layer of silicon dioxide.

12. The method of claim 7, wherein said first and second devices are one of planar field-effect transistors or FinFET transistors.

13. A method of forming first and second semiconductor devices above a common semiconductor substrate, comprising:

forming first and second gate structures above said substrate, wherein each of said first and second gate structures are each positioned between spaced-apart spacers, and wherein each of said first and second gate structures comprises a first layer of gate insulation material positioned above said substrate and a sacrificial gate electrode material positioned above said first layer of insulating material;

forming a first patterned mask layer that covers said first device but exposes said second device for further processing;

performing at least one first etching process through said first patterned mask layer to remove said second gate structure while said first gate structure is masked, said etching process resulting in a gate cavity for said second semiconductor device wherein a portion of said substrate is exposed;

with said first patterned mask layer in position, forming a layer of high-k insulation material in said gate cavity of said second semiconductor device and above said first patterned mask layer;

performing at least one process operation to remove said first patterned mask layer and portions of said layer of high-k insulation material positioned outside of said gate cavity of said second semiconductor device so as to thereby define a high-k gate insulation layer for said second device that is positioned above said exposed portion of said substrate;

forming a second patterned mask layer that covers said second device but exposes said first device for further processing;

performing at least one second etching process through said second patterned mask layer to remove said sacrificial gate electrode of said first gate structure while said second device is masked, said etching process resulting in a gate cavity for said first semiconductor device that is positioned above said first layer of gate insulation material;

removing said second patterned mask layer; and

performing at least one common process operation to form a first metal-containing gate electrode structure for said first semiconductor device and a second metal-containing gate electrode structure for said second semiconductor device, wherein a portion of said first metal-containing gate electrode structure is formed on and in contact with said first layer of gate insulation material and a portion of said second metal-containing gate electrode structure is formed on and in contact with said high-k insulation material.

14. The method of claim 13, wherein performing said at least one common process operation to form a first metal-containing gate electrode structure for said first semiconductor device and a second metal-containing gate electrode structure for said second semiconductor device comprises performing a common metal deposition process to form a work function adjusting metal layer on and in contact with said first layer of gate insulation material and on and in contact with said high-k insulation material.

15. The method of claim 14, further comprising performing at least one additional metal deposition process to form at least one additional layer of metal on said work function adjusting metal layer.

16. The method of claim 13, wherein performing said at least one common process operation to form a first metal-containing gate electrode structure for said first semiconductor device and a second metal-containing gate electrode structure for said second semiconductor device comprises:

performing a plurality of metal deposition processes to form a plurality of metal layers, wherein one of said plurality of metal layers is formed on and in contact with said first layer of gate insulation material and on and in contact with said high-k insulation material; and

performing at least one chemical mechanical planarization process.

17. The method of claim 13, wherein said first layer of gate insulation material is comprised of a layer of silicon dioxide.

18. A device, comprising:

a semiconductor substrate;

a first semiconductor device formed in and above said substrate, said first semiconductor device having a first gate structure comprised of;

a layer of insulating material having a dielectric constant less than 7 positioned above said substrate, said layer of insulating material having a first substantially uniform thickness; and

a first portion of a first metal layer positioned on and in contact with said layer of insulating material; and

a second semiconductor device formed in and above said substrate, said second semiconductor device having a second gate structure comprised of;

a layer of high-k insulation material positioned above said substrate, said layer of high-k insulation material having a second substantially uniform thickness that is less than said first substantially uniform thickness of said layer of insulating material; and

a second portion of said first metal layer positioned on and in contact with said layer of high-k insulation material.

19. The device of claim 18, wherein said layer of insulating material is made of silicon dioxide.

20. The device of claim 18, further comprising an interfacial layer of silicon dioxide positioned between said substrate and said layer of insulating material.

21. The device of claim 18, wherein said first and second semiconductor devices are one of planar field-effect transistors or FinFET transistors.