APPARATUSES HAVING A FERROELECTRIC FIELD-EFFECT TRANSISTOR MEMORY ARRAY AND RELATED METHOD
First Claim
1. An apparatus, comprising:
- a plurality of field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture;
a plurality of gates extending vertically and spaced horizontally between the plurality of FET structures; and
a ferroelectric material separating the plurality of FET structures and the plurality of gates, wherein individual ferroelectric FETs (FeFETs) are formed at intersections the plurality of FET structures, the plurality of gates, and the ferroelectric material.
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Accused Products
Abstract
An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to faun a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates.
100 Citations
33 Claims
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1. An apparatus, comprising:
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a plurality of field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture; a plurality of gates extending vertically and spaced horizontally between the plurality of FET structures; and a ferroelectric material separating the plurality of FET structures and the plurality of gates, wherein individual ferroelectric FETs (FeFETs) are formed at intersections the plurality of FET structures, the plurality of gates, and the ferroelectric material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24)
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10. An apparatus, comprising:
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a first vertical ferroelectric field-effect transistor (FeFET) stack including a first plurality gates separated from a first FET structure by a first ferroelectric material; and a second vertical FeFET stack including a second plurality gates separated from a second FET structure by a second ferroelectric material, wherein the first vertical FeFET stack and the second FeFET stack are stacked horizontally and separated by a dielectric material. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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25. An apparatus, comprising:
a ferroelectric field-effect transistor (FeFET) memory array having a plurality of FeFETs coupled at cross points of a plurality of access lines, wherein the FeFET memory array is configured to have a substantially uniform series resistance for a current path for each FeFET of the plurality of FeFETs. - View Dependent Claims (26)
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27. An apparatus, comprising:
a three-dimensional memory array having a plurality of ferroelectric field-effect transistor (FeFET) memory cells formed at intersections of ferroelectric material coupled with a plurality of bit lines and a plurality of word lines. - View Dependent Claims (28, 29, 30, 31)
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32. A method of operating a three-dimensional ferroelectric field-effect transistor (FeFET) memory array, the method comprising:
applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells of a three-dimensional FeFET memory array, at least one digit line having plurality of FeFET memory cells accessible by neighboring gates. - View Dependent Claims (33)
Specification