THIN-FILM TRANSISTOR ARRAY SUBSTRATE, ORGANIC LIGHT-EMITTING DISPLAY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE THIN-FILM TRANSISTOR ARRAY SUBSTRATE

• US 20140346458A1
• Filed: 10/23/2013
• Published: 11/27/2014
• Est. Priority Date: 05/24/2013
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Park, Jong-Hyun, You, Chun-Gi, Heo, Seong-Kweon, Kim, Jeong-Hwan
• Granted Patent: US 9,184,188 B2
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H10K 50/844 Encapsulations
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/873 Encapsulations

Abstract

A thin-film transistor (“TFT”) array substrate includes: a TFT including an active layer, a gate electrode, a source electrode, a drain electrode, a first insulating layer disposed between the active layer and the gate electrode, and a second insulating layer disposed between the gate electrode, and the source and drain electrode; a pixel electrode including a transparent conductive oxide and disposed in an opening defined in the second insulating layer; a capacitor including a first electrode disposed on a layer on which the active layer is disposed, and a second electrode disposed on a layer on which the gate electrode is disposed; a pad electrode disposed on the second insulating layer and including a material substantially the same as a material in the source electrode and the drain electrode; a first protective layer disposed on the pad electrode; and a second protective layer disposed on the first protective layer.

Claims

1. A thin-film transistor array substrate comprising:

a thin-film transistor comprising;

an active layer;

a gate electrode disposed on the active layer;

a source electrode connected to a source region of the active layer;

a drain electrode connected to a drain region of the active layer;

a first insulating layer disposed between the active layer and the gate electrode; and

a second insulating layer disposed between the gate electrode and the source electrode, and between the gate electrode and the drain electrode;

a pixel electrode disposed in an opening defined in the second insulating layer, wherein the pixel electrode comprises a transparent conductive oxide, and;

a capacitor comprising;

a first electrode disposed on a layer, on which the active layer is disposed; and

a second electrode disposed on a layer, on which the gate electrode is disposed;

a pad electrode disposed on the second insulating layer, wherein the pad electrode comprises a material substantially the same as a material in the source electrode and the drain electrode;

a first protective layer disposed on the pad electrode; and

a second protective layer disposed on the first protective layer.

2. The thin-film transistor array substrate of claim 1, wherein the first protective layer comprises an amorphous transparent conductive oxide.

3. The thin-film transistor array substrate of claim 2, wherein the transparent conductive oxide comprises at least one of indium tin oxide, indium zinc oxide, zinc oxide (ZnO), indium oxide (In₂O₃), indium gallium oxide and aluminum zinc oxide.

4. The thin-film transistor array substrate of claim 1, wherein the second protective layer comprises a polycrystalline transparent conductive oxide.

5. The thin-film transistor array substrate of claim 1, wherein the pad electrode comprises a plurality of metal layers having different electron mobilities from each other.

6. The thin-film transistor array substrate of claim 5, wherein the plurality of metal layers comprises:

a layer comprising molybdenum; and

a layer comprising aluminum.

7. The thin-film transistor array substrate of claim 1, wherein the first protective layer is disposed on the source and drain electrodes.

8. The thin-film transistor array substrate of claim 7, wherein the first protective layer is disposed between the second protective layer and the source electrode, and between the second protective layer and the drain electrode.

9. The thin-film transistor array substrate of claim 1, wherein the active layer comprises a semiconductor material doped with ion impurities.

10. The thin-film transistor array substrate of claim 1, wherein the first electrode comprises a semiconductor material doped with ion impurities.

11. The thin-film transistor array substrate of claim 1, wherein the second electrode and the second insulating layer are spaced apart from each other by a gap.

12. The thin-film transistor array substrate of claim 1, wherein the gate electrode comprises:

a first layer comprising a transparent conductive oxide; and

a second layer comprising a metal.

13. The thin-film transistor array substrate of claim 1, wherein the gate electrode, the source electrode and the drain electrode comprise substantially a same material as each other.

14. An organic light-emitting display apparatus comprising:

a thin-film transistor comprising;

an active layer;

a gate electrode disposed on the active layer;

a source electrode connected to a source region of the active layer;

a drain electrode connected to a drain region of the active layer;

a first insulating layer disposed between the active layer and the gate electrode; and

a second insulating layer disposed between the gate electrode and the source electrode, and between the gate electrode and the drain electrode;

a pixel electrode comprising a transparent conductive oxide, and disposed in an opening defined in the second insulating layer;

a capacitor comprising;

a first electrode disposed on a layer, on which the active layer is disposed; and

a second electrode disposed on a layer, on which the gate electrode is disposed;

a pad electrode disposed on the second insulating layer, and comprising a material substantially the same as a material in the source electrode and the drain electrode;

a first protective layer disposed on the pad electrode;

a second protective layer disposed on the first protective layer;

a third insulating layer disposed on the second insulating layer, wherein an opening is defined in the third insulating layer, and the opening in the third insulating layer exposes the pixel electrode;

an organic emission layer disposed on the pixel electrode; and

an opposite electrode disposed on the organic emission layer.

15. The organic light-emitting display apparatus of claim 14, wherein

the first protective layer comprises an amorphous transparent conductive oxide, and

the second protective layer comprises a polycrystalline transparent conductive oxide.

16. The organic light-emitting display apparatus of claim 14, wherein the first protective layer and the second protective layer are disposed on the source electrode and the drain electrode.

17. The organic light-emitting display apparatus of claim 14, wherein the opposite electrode is a reflective electrode.

18. A method of manufacturing a thin-film transistor array substrate, the method comprising:

providing a semiconductor layer on a substrate, and patterning the semiconductor layer to provide an active layer of a thin-film transistor and a first electrode of a capacitor;

providing a first insulating layer on the patterned semiconductor layer;

providing a transparent conductive oxide layer and a first metal layer on the first insulating layer, and patterning the transparent conductive oxide layer and the first metal layer to provide a pixel electrode, a gate electrode of the thin-film transistor, and a second electrode of the capacitor;

providing a second insulating layer on the patterned transparent conductive oxide layer and the patterned first metal layer, forming openings through the first insulating layer and the second insulating layer to expose source and drain regions of the active layer, and forming openings through the second insulating layer to expose the pixel electrode and the second electrode of the capacitor;

providing a second metal layer and a first protective layer on the second insulating layer, and patterning the second metal layer and the first protective layer to form a source electrode, a drain electrode and a pad electrode, wherein the source electrode and the drain electrode are connected to the source and drain regions of the active layer through the openings which expose the source and drain regions of the active layer;

providing a third insulating layer on the patterned second metal layer and the patterned first protective layer, and forming openings through the third insulating layer to expose the pixel electrode and the pad electrode; and

providing a second protective layer on the first protective layer.

19. The method of claim 18, wherein the first metal layer and the second metal layer comprise substantially a same material as each other.

20. The method of claim 18, wherein the second metal layer comprises a plurality of metal layers having different electron mobilities from each other.

21. The method of claim 18, wherein the first protective layer comprises an amorphous transparent conductive oxide.

22. The method of claim 18, wherein the second protective layer comprises a polycrystalline transparent conductive oxide.

23. The method of claim 18, wherein the providing the second protective layer on the first protective layer comprises performing plasma treatment on the first protective layer.

24. The method of claim 23, wherein the plasma treatment is performed after the first protective layer on the pad electrode is exposed through the third insulating layer.

25. The method of claim 18, wherein the providing the second protective layer on the first protective layer comprises thermally annealing the first protective layer.

26. The method of claim 25, wherein the thermal annealing is performed before the first protective layer on the pad electrode is exposed through the third insulating layer.