Semiconductor Device, Method of Manufacturing a Semiconductor Device and Integrated Circuit

• US 20140346590A1
• Filed: 05/24/2013
• Published: 11/27/2014
• Est. Priority Date: 05/24/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Meiser, Andreas, Schloesser, Till, Hirler, Franz
• Granted Patent: US 9,620,637 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66204 Diodes
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device formed in a semiconductor substrate includes a source region, a drain region, a gate electrode, and a body region disposed between the source region and the drain region. The gate electrode is disposed adjacent at least two sides of the body region, and the source region and the gate electrode are coupled to a source terminal. A width of the body region between the two sides of the body region is selected so that the body region is configured to be fully depleted.

Claims

1. A semiconductor device in a semiconductor substrate, comprising:

a source region, a drain region, a gate electrode, and a body region disposed between the source region and the drain region,

the gate electrode being disposed adjacent at least two sides of the body region,

the source region and the gate electrode being coupled to a source terminal, and

wherein a width of the body region measured between the two sides of the body region is selected so that the body region is configured to be fully depleted.

2. The semiconductor device according to claim 1, wherein the source region is disposed adjacent to a first main surface of the semiconductor substrate, the drain region is disposed adjacent to a second main surface of the semiconductor substrate, and the body region extends in a direction intersecting the first main surface.

3. The semiconductor device according to claim 2, wherein the gate electrode is disposed in trenches extending into the semiconductor substrate at the first main surface.

4. The semiconductor device according to claim 3, wherein a distance d between adjacent trenches corresponds to the width of the body region and fulfills the following relationship:

d<

2*l_d, wherein l_d denotes a maximum length of a depletion zone which is formed at an interface between the body region and a gate dielectric adjacent to the gate electrode.

5. The semiconductor device according to claim 3, further comprising a field plate disposed in a bottom portion of the trenches and insulated from the semiconductor substrate by a field dielectric layer.

6. The semiconductor device according to claim 1, wherein the width d of the body region fulfills the following relationship:

d<

2*l_d, wherein l_d denotes a maximum length of a depletion zone which is formed at an interface between the body region and a gate dielectric adjacent to the gate electrode.

7. The semiconductor device according to claim 1, wherein a ratio of a length to the width of the body region is larger than 2.5, the length being measured along a current path in an extension direction of the gate electrode.

8. The semiconductor device according to claim 1, wherein the source region and the drain region are doped with dopants of a first conductivity type, the body region is doped with dopants of a second conductivity type,

the semiconductor device further comprising a drain extension region doped with dopants of the first conductivity type, the drain extension region being disposed between the body region and the drain region.

9. The semiconductor device according to claim 1, wherein the body region is coupled to the source terminal.

10. The semiconductor device according to claim 1, wherein a thickness of a gate dielectric layer between the gate electrode and the body region is more than 10 nm.

11. An integrated circuit comprising a first semiconductor device formed in a semiconductor substrate, the semiconductor device comprising:

a source region, a drain region, a gate electrode, and a body region disposed between the source region and the drain region,

the source region being disposed adjacent to a first main surface of the semiconductor substrate, the drain region being disposed adjacent to a second main surface of the semiconductor substrate, and the body region extending in a direction intersecting the first main surface,

the gate electrode being disposed in trenches extending into the semiconductor substrate at the first main surface,

the body region being disposed between adjacent trenches,

the source region and the gate electrode being coupled to a source terminal, and

wherein a distance between adjacent trenches is such that the body region is configured to be fully depleted.

12. The integrated circuit of claim 11, further comprising a second semiconductor device formed in the semiconductor substrate, the second semiconductor device comprising:

a second source region, a second drain region, a second gate electrode, and a second body region disposed between the second source region and the second drain region,

the second source region and the second drain region being doped with dopants of a first conductivity type,

the second body region being doped with dopants of a second conductivity type,

the second source region being disposed adjacent to the first main surface of the semiconductor substrate, the second drain region being disposed adjacent to the second main surface of the semiconductor substrate, and the second body region extending in a direction intersecting the first main surface,

the second gate electrode being disposed in second trenches arranged in the first main surface,

the second source region and the second gate electrode being coupled to the source terminal, and

a doped portion of the second conductivity type being arranged between the first semiconductor device and the second semiconductor device.

13. The integrated circuit of claim 12, further comprising a clamping portion doped with dopants of the first or second conductivity type at a higher concentration than the doped portion between the first and the second semiconductor device.

14. The integrated circuit of claim 11, further comprising a further semiconductor device in the semiconductor substrate.

15. The integrated circuit according to claim 11, further comprising a field plate disposed in a bottom portion the trenches and insulated from the semiconductor substrate by a field dielectric layer.

16. The integrated circuit according to claim 15, further comprising a further semiconductor device in the semiconductor substrate, the further semiconductor device comprising further trenches, wherein a field plate and a gate electrode of the further semiconductor device is disposed in the further trenches.

17. The integrated circuit according to claim 11, wherein the distance d between adjacent trenches corresponds to a width of the body region and fulfills the following relationship:

d<

2*l_d, wherein l_d denotes a maximum length of a depletion zone which is formed at an interface between the body region and a gate dielectric adjacent to the gate electrode and the body width d corresponds to the width of the body region measured perpendicularly to the gate electrode.

18. The integrated circuit according to claim 11, wherein the distance d between adjacent trenches corresponds to a width of the body region and a ratio of a length to the width of the body region is larger than 2.5, the length being measured along a current path in an extension direction of the gate electrode.

19. The integrated circuit according to claim 11,

wherein the source region and the drain region are doped with dopants of a first conductivity type, the body region is doped with dopants of a second conductivity type,

the integrated circuit further comprising a drain extension region doped with dopants of the second conductivity type, the drain extension region being disposed between the body region and the drain region.

20. The integrated circuit according to claim 11, wherein the body region is coupled to the source terminal.

21. The integrated circuit according to claim 11, wherein a thickness of a gate dielectric layer between the gate electrode and the body region is more than 10 nm.

22. The integrated circuit according to claim 14, wherein the further device is selected from the group consisting of a MOSFET, a flyback diode, a driver circuit, and a CMOS circuit.

23. A method of manufacturing a semiconductor device in a semiconductor substrate, the method comprising:

forming a source region, a drain region and a gate electrode;

forming a body region between the source region and the drain region,

wherein forming the gate electrode is accomplished so that the gate electrode is disposed adjacent at least two sides of the body region, and a width of the body region measured between the two sides of the body region is selected so that the body region is configured to be fully depleted; and

coupling the source region and the gate electrode to a source terminal.

24. The method according to claim 23, wherein the source region is formed adjacent to a first main surface of the semiconductor substrate, the drain region is formed adjacent to a second main surface of the semiconductor substrate and the body region is formed so as to extend in a direction intersecting the first main surface.

25. The method according to claim 24, wherein forming the gate electrode comprises etching trenches in the first main surface and filling a conductive material in the trenches.