Tuning Tensile Strain on FinFET

• US 20140346607A1
• Filed: 05/23/2013
• Published: 11/27/2014
• Est. Priority Date: 05/23/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Chen, Guan-Lin, Lin, Zhi-Chang, Hsu, Ting-Hung, Huang, Jiun-Jia
• Granted Patent: US 9,153,668 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/02356 treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.

Claims

1. A method of tuning tensile strain in an integrated circuit, comprising:

forming a source/drain region on opposing sides of a gate region in a fin;

forming spacers over the fin, the spacers adjacent to the source/drain regions;

depositing a dielectric between the spacers; and

performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.

2. The method of claim 1, further comprising performing the annealing process at a temperature of between about 500°

C. to about 650°

C.

3. The method of claim 1, further comprising performing the annealing process for a time of between about 60 minutes to about 120 minutes.

4. The method of claim 1, further comprising performing the annealing process at a pressure of about 1 atmosphere.

5. The method of claim 1, further comprising performing the annealing process to shrink the dielectric between about 15% to about 18% relative to a size of the dielectric prior to the annealing process.

6. The method of claim 1, further comprising performing the annealing process to reduce a height and a width of the dielectric.

7. The method of claim 1, further comprising performing the annealing process to outgas at least one of nitrogen and hydrogen from the dielectric.

8. The method of claim 1, further comprising constructing a gate electrode structure over the gate region as expanded and between the spacers as deformed.

9. The method of claim 1, further comprising contracting the dielectric to draw opposing ones of the spacers closer to each other.

10. The method of claim 1, further comprising deforming the spacer inwardly toward the dielectric, a middle portion of the spacer deformed more than top and bottom portions of the spacer.

11. A fin field effect transistor (FinFET) having a tunable tensile strain, comprising:

a source/drain region on opposing sides of an enlarged gate region in a fin;

a contracted dielectric disposed over the source/drain regions; and

spacers disposed over the fin, an amount of deformation of the spacers due to the contracted dielectric and contributing to a length of the enlarged gate region in the fin.

12. The FinFET of claim 11, wherein a contour of the contracted dielectric is equivalent to a contour of the spacers.

13. The FinFET of claim 11, wherein the contracted dielectric has been reduced in size about 15% to about 18% relative to an original size of the contracted dielectric.

14. The FinFET of claim 11, wherein the contracted dielectric is vertically aligned with the source/drain regions.

15. The FinFET of claim 11, wherein the spacers are laterally adjacent to the enlarged gate region and the source/drain regions and on opposing sides of the contracted dielectric.

16. The FinFET of claim 11, wherein a gate electrode structure is disposed over the gate region, the gate electrode structure including an interfacial oxide, a high-k dielectric, and a metal gate.

17. An integrated circuit having a tunable tensile strain, comprising

a p-type metal-oxide-semiconductor (PMOS) device with a first gate region;

and

an n-type metal-oxide-semiconductor (NMOS) device adjacent the PMOS device, the NMOS device including deformed spacers on opposing sides of a contracted dielectric, the deformed spacers adjacent a second gate region, a length of the second gate region greater than a length of the first gate region.

18. The integrated circuit device of claim 17, wherein a height of a second gate in the NMOS device is less than a height of a first gate in the PMOS device.

19. The integrated circuit device of claim 17, wherein the PMOS device includes straight spacers on opposing sides of a dielectric.

20. The integrated circuit device of claim 19, wherein the contracted dielectric and the dielectric are formed from different materials.