SURFACE MOUNTABLE ELECTRONIC COMPONENT

• US 20140346642A1
• Filed: 09/06/2012
• Published: 11/27/2014
• Est. Priority Date: 09/06/2011
• Status: Active Grant

• Current Assignee: Vishay Semiconductor GmbH (Vishay Intertechnology Incorporated)
• Original Assignee: Vishay Semiconductor GmbH (Vishay Intertechnology Incorporated)
• Inventors: Mhner, Claus
• Granted Patent: US 10,629,485 B2
• Time in Patent Office: Days
• US Class Current: 257/620
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1451 Function
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER

Abstract

A surface mountable electronic component free of connecting wires comprises a semiconductor substrate, wherein a plurality of solderable connection areas are arranged at the underside of the component. The component comprises at least one recess is formed in the region of the edges bounding the underside; and in that the recess is covered with an insulating layer. A method for the manufacture of such a component comprises the formation of corresponding recesses.

Claims

1. A surface mountable electronic component free of connecting wires having a semiconductor substrate, wherein a plurality of solderable connection areas are arranged at the an underside of the component,

wherein

at least one recess is formed in a region of the edges bounding the underside;

and wherein the recess is covered with an insulating layer.

2. A component in accordance with claim 1,

wherein

the component has connection areas exclusively at its underside.

3. A component in accordance with claim 1, wherein

the semiconductor substrate is manufactured by means of a planar process.

4. A component in accordance with claim 1,

wherein

the maximum depth of the recess amounts to at least 5 μ

m and to at most 40 μ

m.

5. A component in accordance with claim 1,

wherein

the maximum depth of the recess amounts to at least 2% and at most 10% of the height of the component.

6. A component in accordance with claim 1,

wherein

the maximum depth of the recess corresponds to the width of the recess or is less than the width.

7. A component in accordance with claim 1,

wherein

the recess is designed as a hollow groove.

8. A component in accordance with claim 1,

wherein

the recess comprises a planar shoulder section which is inclined with respect to a plane defined by the underside of the component.

9. A component in accordance with claim 8,

wherein

the recess further comprises a base section which bounds the inclined shoulder section on the one side and a side surface of the semiconductor substrate at the other side.

10. A component in accordance with claim 1,

wherein

the insulation layer comprises at least one of silicon oxide, silicon nitride, paint or an adhesive.

11. A component in accordance with claim 1,

wherein

the thickness of the insulation layer amounts to less than 2 μ

m.

12. A component in accordance with claim 1,

wherein

the component has at least one side surface which extends between the recess and an upperside of the component and which is not electrically insulated for the completed component.

19. A component in accordance with claim 4, wherein the maximum depth of the recess amounts to approximately 10 to 15 μ

m.

20. A component in accordance with claim 5,

wherein the maximum depth of the recess amounts to between approximately 3% to 6% of the height of the component.

21. A component in accordance with claim 8,

wherein the degree of inclination of the planar shoulder section with respect to said plane amounts to 30°

to 80°

.

22. A component in accordance with claim 8,

wherein the degree of inclination of the planar shoulder section with respect to said plane amounts to approximately 60°

.

23. A component in accordance with claim 9,

wherein said base section runs in parallel to the plane defined by the underside of the semiconductor substrate.

24. A component in accordance with claim 11,

wherein the thickness of the insulation layer amounts to less than 1 μ

m.

13. A method for the manufacture of surface mountable electronic components free of connecting wires, which each have a semiconductor substrate, and each have a plurality of solderable connection areas arranged at their respective underside,

comprising the steps of:

forming recesses at a first surface of a wafer composed of a semiconductor substrate material, wherein the recesses extend along separation lines which separate a component from an adjacent component;

applying an insulation layer on the wafer which covers at least the recesses; and

separating the components along the separation lines.

14. A method in accordance with claim 13,

wherein

the recesses are formed by means of an etching process.

15. A method in accordance with claim 13,

wherein

the step of forming the recesses and a step of forming marking codes at a second surface of the wafer lying opposite to said first surface takes place in a same method step.

16. A method in accordance with claim 13,

wherein

the insulation layer is applied by means of chemical vapor deposition.

17. A method in accordance with claim 13,

further comprising the step of forming

active structures in each of the components prior to the step of separating the components, wherein the separation of the components along the separation lines takes place outside of the active structures.

18. A method for connecting a surface mountable electronic component to a circuit board, wherein the surface mountable electronic component is free of connection wires and has a semiconductor substrate, wherein a plurality of solderable connection areas are arranged at an underside of the component, wherein at least one recess is formed in a region of the edges bounding the underside and wherein the recess is covered with an insulating layer, and wherein the circuit board has a plurality of contacting surfaces which are associated with respective connection areas of the component, comprising the steps of:

applying a solder at at least one of the connection areas and at the contacting surfaces;

positioning the component at the circuit board; and

melting the solder so that each connection area is connected to the associated contacting surface by means of the solder.