SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND HIGH-FREQUENCY POWER AMPLIFIER MODULE

• US 20140347130A1
• Filed: 12/05/2012
• Published: 11/27/2014
• Est. Priority Date: 12/20/2011
• Status: Active Grant

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Murata Manufacturing Co Limited
• Inventors: Iijima, Masanori, Morisawa, Fuminori
• Granted Patent: US 9,166,531 B2
• Time in Patent Office: Days
• US Class Current: 330/288
• CPC Class Codes: H03F 1/0233 by using a signal derived from the output signal, e.g. bootstrapping the voltage supply
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/111 the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/27 A biasing circuit node being switched in an amplifier circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/429 Two or more amplifiers or one amplifier with filters for different frequency bands are coupled in parallel at the input or output
• CPC Class Codes: H03F 2200/528 the temperature dependence being controlled by referencing to the band gap
• CPC Class Codes: H03F 2200/78 A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2203/45112 the biasing of the differential amplifier being controlled from the input or the output signal
• CPC Class Codes: H03F 2203/45398 the AAC comprising a voltage generating circuit as bias circuit for the AAC
• CPC Class Codes: H03F 2203/45528 the FBC comprising one or more passive resistors and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45542 the IC comprising bias stabilisation means, e.g. DC level stabilisation, and temperature coefficient dependent control, e.g. by DC level shifting
• CPC Class Codes: H03F 2203/45594 the IC comprising one or more resistors, which are not biasing resistor
• CPC Class Codes: H03F 2203/45601 the IC comprising one or more passive resistors by feedback
• CPC Class Codes: H03F 2203/45622 the IC comprising a voltage generating circuit
• CPC Class Codes: H03F 2203/45674 the LC comprising one current mirror
• CPC Class Codes: H03F 2203/45726 : the LC comprising more than one switch, which are not cross coupled
• CPC Class Codes: H03F 2203/7206 : the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias voltage in the amplifier
• CPC Class Codes: H03F 2203/7209 : the gated amplifier being switched from a first band to a second band
• CPC Class Codes: H03F 2203/7236 : the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/193 : with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/213 : in integrated circuits
• CPC Class Codes: H03F 3/245 : with semiconductor devices only
• CPC Class Codes: H03F 3/45 : Differential amplifiers differential sense amplifiers G11C7/062
• CPC Class Codes: H03F 3/45071 : with semiconductor devices only
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 : using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0088 : using discontinuously variable devices, e.g. switch-operated

Abstract

The invention provides a semiconductor integrated circuit device and a high-frequency power amplifier module capable of reducing variations in the transmission power characteristics. The semiconductor integrated circuit device and the high-frequency power amplifier module each include, for example, a bandgap reference circuit, a regulator circuit, and a reference-voltage correction circuit which is provided between the bandgap reference circuit and the regulator circuit and which includes a unity gain buffer. The reference-voltage correction circuit corrects variations in a bandgap voltage from the bandgap reference circuit. The reference-voltage correction circuit includes first to third resistance paths having mutually different resistance values, and corrects the variations by selectively supplying a current which reflects an output voltage of the unity gain buffer to any one of the first to third resistance paths. The selection in this case is performed by connecting a bonding wire to any one of the terminals REF1 to REF3.

Claims

1. A semiconductor integrated circuit device comprising:

a reference-voltage generating circuit configured to generate a first reference voltage;

a reference-voltage correction circuit supplied with the first reference voltage and configured to generate a second reference voltage obtained by correcting the first reference voltage; and

a regulator circuit including a first amplifier circuit of a negative feedback configuration and a feedback resistor, and configured to generate a predetermined output voltage according to the second reference voltage and a resistance value of the feedback resistor, wherein

the reference-voltage correction circuit includes;

a buffer circuit supplied with the first reference voltage, and configured to output a first voltage with a potential approximately equal to that of the first reference voltage and perform impedance conversion between an input and an output;

a first resistor configured to generate a first current having a current value according to a voltage value of the first voltage;

a first node supplied with a second current having a current value proportional to the current value of the first current; and

first, second, and third resistance paths selectively coupled between the first node and a first power supply voltage and having mutually different resistance values, and

the second reference voltage is generated in the first node on the basis of a resistance value associated with any one resistance path selected from among the first, second, and third resistance paths and the current value of the second current.

2. The semiconductor integrated circuit device according to claim 1, wherein

the buffer circuit includes:

a second amplifier circuit having a first input node supplied with the first reference voltage; and

a first transistor configured to be controlled by an output of the second amplifier circuit, one end of the first transistor being coupled to a second input node of the second amplifier circuit and to the first resistor, and

the second current is supplied to the first node via a second transistor current-mirror connected to the first transistor.

3. The semiconductor integrated circuit device according to claim 2, wherein

the semiconductor integrated circuit device is realized by one semiconductor chip,

the semiconductor chip further includes first, second, and third terminals,

the first resistance path is realized by a first resistor coupled between the first node and the first terminal,

the second resistance path is realized by a second resistor coupled between the first node and the second terminal,

the third resistance path is realized by a third resistor coupled between the first node and the third terminal, and

selection of the first, second, and third resistance paths is realized by connecting any one of the first, second, and third terminals, via a bonding wire, to a supply area of the first power supply voltage provided outside the semiconductor chip.

4. The semiconductor integrated circuit device according to claim 3, wherein the semiconductor chip further includes:

a fourth terminal;

a first switch and a fourth resistor coupled in series between an output node of the regulator circuit and the fourth terminal; and

a second switch and a fifth resistor coupled in series between the output node of the regulator circuit and the fourth terminal and coupled in parallel to the first switch and the fourth resistor, and

the fourth terminal is configured to be used for setting a bias of a power amplifier transistor.

5. The semiconductor integrated circuit device according to claim 2, wherein

the reference-voltage generating circuit is a bandgap reference circuit.

6. The semiconductor integrated circuit device according to claim 2, wherein

the semiconductor integrated circuit device is configured by one semiconductor chip,

the semiconductor chip further includes first, second, and third terminals,

the first resistance path is realized by a first resistor coupled between the first node and the first terminal,

the second resistance path is realized by a second resistor coupled between the first node and the second terminal,

the third resistance path is realized by a third resistor coupled between the first node and the third terminal, and

selection of the first, second, and third resistance paths is realized by connecting any one of the first, second, and third terminals, via a bonding wire, to a supply terminal of the first power supply voltage provided inside the semiconductor chip.

7. The semiconductor integrated circuit device according to claim 2, wherein

the semiconductor integrated circuit device is configured by one semiconductor chip,

the semiconductor chip includes fifth and sixth terminals,

the first resistance path is realized by a sixth resistor coupled between the first node and the fifth terminal,

the second and third resistance paths are realized by:

seventh and eighth resistors coupled in series between the first node and the sixth terminal; and

a fuse coupled in parallel to the eighth resistor,

selection of the first resistance path is realized by connecting the fifth terminal, via a bonding wire, to a supply terminal of the first power supply voltage provided inside or outside the semiconductor chip,

selection of the second resistance path is realized by connecting the sixth terminal, via a bonding wire, to a supply terminal of the first power supply voltage provided inside or outside the semiconductor chip, and

selection of the third resistance path is realized by connecting the sixth terminal, via a bonding wire, to a supply terminal of the first power supply voltage provided inside or outside the semiconductor chip, and also by disconnecting the fuse.

8. A semiconductor integrated circuit device comprising:

a reference-voltage generating circuit configured to generate a first reference voltage;

a first amplifier circuit having a first input node supplied with the first reference voltage;

a first transistor configured to be controlled by an output of the first amplifier circuit, one end of the first transistor being coupled to a second input node of the first amplifier circuit;

first, second, and third resistance paths selectively coupled between the second input node and a first power supply voltage, and having mutually different resistance values; and

a second transistor current-mirror connected to the first transistor.

9. The semiconductor integrated circuit device according to claim 8, wherein

the semiconductor integrated circuit device is realized by one semiconductor chip,

the semiconductor chip further includes first, second, and third terminals,

the first resistance path is realized by a first resistor coupled between the second input node and the first terminal,

the second resistance path is realized by a second resistor coupled between the second input node and the second terminal,

the third resistance path is realized by a third resistor coupled between the second input node and the third terminal, and

selection of the first, second, and third resistance paths is realized by connecting any one of the first, second, and third terminals, via a bonding wire, to a supply area of the first power supply voltage provided outside the semiconductor chip.

10. The semiconductor integrated circuit device according to claim 9, wherein

a current flowing in the second transistor sets a bias of a power amplifier transistor.

11. The semiconductor integrated circuit device according to claim 9, wherein

the reference-voltage generating circuit is a bandgap reference circuit.

12. The semiconductor integrated circuit device according to claim 9, wherein

the semiconductor integrated circuit device is realized by one semiconductor chip,

the semiconductor chip further includes first, second, and third terminals,

the first resistance path is realized by a first resistor coupled between the second input node and the first terminal,

the second resistance path is realized by a second resistor coupled between the second input node and the second terminal,

the third resistance path is realized by a third resistor coupled between the second input node and the third terminal, and

selection of the first, second, and third resistance paths is realized by connecting any one of the first, second, and third terminals, via a bonding wire, to a supply terminal of the first power supply voltage provided inside the semiconductor chip.

13. A high-frequency power amplifier module comprising a module wiring substrate on which one or more semiconductor chips are mounted, wherein

on the one or more semiconductor chips, there are formed:

a plurality of power amplifier transistors; and

a control block configured to supply a bias to the plurality of power amplifier transistors, the control block includes;

a reference-voltage generating circuit configured to generate a first reference voltage;

a reference-voltage correction circuit supplied with the first reference voltage and configured to generate a second reference voltage obtained by correcting the first reference voltage; and

a regulator circuit including a first amplifier circuit of a negative feedback configuration and a feedback resistor, and configured to generate a predetermined output voltage according to the second reference voltage and a resistance value of the feedback resistor,

the reference-voltage correction circuit includes;

a buffer circuit supplied with the first reference voltage, and configured to output a first voltage with a potential approximately equal to that of the first reference voltage and perform impedance conversion between an input and an output;

a first resistor configured to generate a first current having a current value according to a voltage value of the first voltage;

a first node supplied with a second current having a current value proportional to the current value of the first current; and

first, second, and third resistance paths selectively coupled between the first node and a first power supply voltage and that have mutually different resistance values,

the second reference voltage is generated in the first node on the basis of a resistance value associated with any one resistance path selected from among the first, second, and third resistance paths and the current value of the second current, and

biases of the plurality of power amplifier transistors are determined according to an output voltage of the regulator circuit.

14. The high-frequency power amplifier module according to claim 13, wherein

the buffer circuit includes:

a second amplifier circuit having a first input node supplied with the first reference voltage; and

a first transistor configured to be controlled by an output of the second amplifier circuit, and one end of the first transistor being coupled to a second input node of the second amplifier circuit and to the first resistor, and

the second current is supplied to the first node via a second transistor current-mirror connected to the first transistor.

15. The high-frequency power amplifier module according to claim 14, wherein

the one or more semiconductor chips further include first, second, and third terminals,

the first resistance path is realized by a first resistor coupled between the first node and the first terminal,

the second resistance path is realized by a second resistor coupled between the first node and the second terminal,

the third resistance path is realized by a third resistor coupled between the first node and the third terminal, and

selection of the first, second, and third resistance paths is realized by connecting any one of the first, second, and third terminals, via a bonding wire, to a supply area of the first power supply voltage provided on the module wiring substrate.

16. The high-frequency power amplifier module according to claim 14, wherein

the one or more semiconductor chips further include:

a second node;

a first switch and a fourth resistor coupled in series between an output node of the regulator circuit and the second node; and

a second switch and a fifth resistor coupled in series between the output node of the regulator circuit and the second node, and coupled in parallel to the first switch and the fourth resistor, and

biases of the plurality of power amplifier transistors are supplied from the second node.

17. The high-frequency power amplifier module according to claim 14, wherein

the reference-voltage generating circuit is a bandgap reference circuit.

18. The high-frequency power amplifier module according to claim 14, wherein

the one or more semiconductor chips further include first, second, and third terminals,

the first resistance path is realized by a first resistor coupled between the first node and the first terminal,

the second resistance path is realized by a second resistor coupled between the first node and the second terminal,

the third resistance path is realized by a third resistor coupled between the first node and the third terminal, and

selection of the first, second, and third resistance paths is realized by connecting any one of the first, second, and third terminals, via a bonding wire, to a supply terminal of the first power supply voltage provided inside the one or more semiconductor chips.