NOR-BASED BCAM/TCAM CELL AND ARRAY WITH NAND SCALABILITY

• US 20140347933A1
• Filed: 08/31/2013
• Published: 11/27/2014
• Est. Priority Date: 08/31/2012
• Status: Active Grant

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter Wung
• Granted Patent: US 9,001,545 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series

Abstract

This invention discloses a 2T-string NOR-based CAM logic cell comprising two physical NAND cells connected in series with two horizontal WLs and one vertical BL and one vertical SL. Additionally, a sector of NOR-based CAM logic cell array is configured with N vertical cell strings each including M 2T-string NOR-based CAM logic cells connected in parallel sharing a local vertical SL and one dedicated vertical ML as an Operand word vertical page. Each 2T-string NOR-based CAM logic cell can be either a binary or ternary CAM cell associated with two or three physical states assigned to NAND cells'"'"' Vt levels for defining CAM logic states. Logic match of M-logic-bit inputs is found for at least one vertical page if the corresponding M 2T-string NOR-based CAM logic cells are in non-conduction state, providing M times faster Compare performance over the NAND-based CAM and 2 time faster than SRAM-based CAM.

Claims

1. A 2T-string NOR-based CAM logic cell circuit with NAND scalability, the 2T-string NOR-based CAM logic cell comprising:

a first NAND flash transistor connected a second NAND flash transistor in series, the first NAND flash transistor including a first gate coupled to a first word line and a drain node coupled to a vertical bit line, the second NAND flash transistor including a second gate coupled to a second word line and a source node coupled to a vertical source line, each of the first NAND flash transistor and the second NAND flash transistor being associated with at least a first threshold voltage level Vt0 of a negative value corresponding to a first physical state or a second threshold voltage level Vt1 of a positive value but smaller than power voltage level VDD corresponding to a second physical state;

wherein the first NAND flash transistor and the second NAND flash transistor respectively corresponding to the first physical state and the second physical state define a first CAM logic state “

0” and

the first NAND flash transistor and the second NAND flash transistor being respectively associated with the second physical state and the first physical state define a second CAM logic state “

1”

, the first word line and the second word line are respectively at either ground voltage VSS=0V level or the complementary VDD level for performing a compare operation to determine if a single logic-bit match is found at either one of the first CAM logic state “

0”

or the second CAM logic state “

1”

when one of the first NAND flash transistor and the second NAND flash transistor is in non-conduction state.

2. The 2T-string NOR-based CAM logic cell circuit of claim 1 wherein each of the first and second NAND flash transistors is a 2-poly floating-gate type NMOS transistor.

3. The 2T-string NOR-based CAM logic cell circuit of claim 1 wherein the first threshold voltage level Vt0 is set below the ground voltage VSS and the second threshold voltage level Vt1 is set greater than VSS and smaller than the power voltage VDD based on Vt0<

VSS<

Vt1<

VDD.

4. The 2T-string NOR-based CAM logic cell circuit of claim 1 wherein the single logic-bit match at the first CAM logic state “

0”

is found if the first word line is at the power voltage VDD level and second word line is at the complementary 0V and no-match is found if the first word line is at 0V and second word line is at the complementary VDD level.

5. The 2T-string NOR-based CAM logic cell circuit of claim 1 wherein the single logic-bit match at the first CAM logic state “

1”

is found if the first word line is at 0V and second word line is at the complementary VDD level and no-match is found if the first word line is at the VDD level and second word line is at the complementary 0V.

6. The 2T-string NOR-based CAM logic cell circuit of claim 1 wherein the single logic-bit is not matched when both the first NAND flash transistor and the second NAND flash transistor are in conduction state.

7. The 2T-string NOR-based CAM logic cell circuit of claim 1 wherein at least one of the first NAND flash transistor and the second NAND flash transistor is further assigned with a third threshold voltage level Vt2 for defining a third CAM logic state “

X”

, the Vt2 level being selected to be a positive value greater than the power voltage VDD level based on Vt0<

VSS<

Vt1<

VDD<

Vt2.

8. The 2T-string NOR-based CAM logic cell circuit of claim 7 wherein the third CAM logic state “

X”

is further associated with a physical state that both the first NAND flash transistor and the second NAND flash transistor are assigned with the third threshold voltage level Vt2 greater than the VDD level.

9. The 2T-string NOR-based CAM logic cell circuit of claim 7 wherein the single logic-bit match is determined to be “

don'"'"'t care”

for the third CAM logic state X wherein a non-conduction state is always associated with at least one of the first NAND flash transistor and the second NAND flash transistor no matter what the first word line and the second word line are respectively at either VSS=0V level or the complementary VDD level during the compare operation.

10. The 2T-string NOR-based CAM logic cell circuit of claim 1 wherein the first physical state is associated with an erased state for any one of the first NAND flash transistor and the second NAND flash transistor and the second physical state is associated with a programmed state for any one of the first NAND flash transistor and the second NAND flash transistor by precharging from the vertical bit line.

11. A sector of M×

N 2T-string NOR-based CAM logic cell array comprising;

a M×

N matrix of 2T-string NOR-based CAM logic cells including M paired horizontal word lines coupled through N vertical pages, M and N being properly selected integer numbers, each paired horizontal word lines including a first word line and a second word line, each of the N vertical pages including M 2T-string NOR-based CAM logic cells connected in parallel sharing a vertical local bit line and a vertical local source line, the vertical local source line being accessed by a horizontal global source line via a first select transistor commonly for the N vertical pages and the vertical local bit line being accessed by a vertical global bit line via a second select transistor individually for each of the N vertical page, each of the M 2T-string NOR-based CAM logic cells comprising;

a first NAND flash transistor connected a second NAND flash transistor in series, the first NAND flash transistor including a first gate coupled to the first word line and a drain node coupled to the vertical local bit line, the second NAND flash transistor including a second gate coupled to the second word line and a source node coupled to the vertical local source line, each of the first NAND flash transistor and the second NAND flash transistor being associated with at least a first threshold voltage level Vt0 of a negative value corresponding to a first physical state or a second threshold voltage level Vt1 of a positive value corresponding to a second physical state, wherein the first NAND flash transistor and the second NAND flash transistor being respectively associated with the first physical state and the second physical state define a first CAM logic state “

0” and

the first NAND flash transistor and the second NAND flash transistor being respectively associated with the second physical state and the first physical state define a second CAM logic state “

1”

;

a search word device configured to generate at least M-bit logic outputs, the M pairs of outputs being respectively coupled to the M paired horizontal word lines, each pair of outputs being either at a ground voltage VSS=0V or at a complementary power voltage VDD level for initiating a compare operation to determine if a single logic-bit match is found for each of the M 2T-string NOR-based CAM logic cells at any one of the first CAM logic state “

0” and

the second CAM logic state “

1”

when one of the first NAND flash transistor and the second NAND flash transistor is in non-conduction state;

a priority decoder device configured to receive N vertical global bit lines respectively associated with the N vertical pages as N match lines for sending a match information to a hit line if at least one M-logic-bit match is found for one vertical page with all the M 2T-string NOR-based CAM logic cells respectively at either one of the first CAM logic state “

0”

or the second CAM logic state “

1” and

generating a priority list if multiple matches are found respectively for corresponding multiple vertical pages; and

a Comparand address generator device coupled to the N match lines and received the match information from the N match lines and the hit line to generate an address list associated with one or more vertical pages having the at least one M-logic-bit match or one or more partial matches depending on the priority list.

12. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 11 wherein each of the first NAND flash transistor and second NAND flash transistor is a 2-poly floating-gate type NMOS transistor.

13. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 11 wherein the first physical state is associated with an erased state for each of the first NAND flash transistor and the second NAND flash transistor, the second physical state is associated with a programmed state for each of the first NAND flash transistor and the second NAND flash transistor precharged from the vertical local bit line through the vertical global bit line.

14. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 11 wherein each of the M 2T-string NOR-based CAM logic cells is a 2T-string NOR-based Binary CAM (BCAM) logic cell wherein each of the first NAND flash transistor and the second NAND flash transistor is assigned the first threshold voltage level Vt0 and the second threshold voltage level Vt1 that are limited by Vt0<

VSS<

Vt1<

VDD for the 2T-string NOR-based BCAM logic cell operated with the power voltage VDD.

15. The sector of M 2T-string NOR-based CAM logic cell array of claim 14 wherein the single logic-bit match is found for the 2T-string NOR-based BCAM logic cell at the first CAM logic state “

0”

if a first word line is at the VDD level and second word line is at the complementary 0V and no-match is found if the first word line is at 0V and second word line is at the complementary VDD level.

16. The sector of M×

M 2T-string NOR-based CAM logic cell array of claim 14 wherein the single logic-bit match is found for the 2T-string NOR-based BCAM logic cell at the first CAM logic state “

1”

if the first word line is at 0V and second word line is at the complementary VDD level and no-match is found if the first word line is at the VDD level and second word line is at the complementary 0V.

17. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 14 wherein the single logic-bit match is not found for the 2T-string NOR-based BCAM logic cell at any one of the first CAM logic state “

0” and

the second CAM logic state “

1”

when both the first NAND flash transistor and the second NAND flash transistor are in conduction state.

18. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 17 wherein the at least one M-logic-bit match is found for one of the N vertical pages when all single logic-bit matches are found for each of the corresponding M 2T-string NOR-based BCAM logic cells at any one of the first CAM logic state “

0” and

the second CAM logic state “

1”

to make the corresponding vertical page in non-conduction state and maintain the corresponding vertical global bit line at a high voltage level, or not found when at least a no-match is found for one of the M 2T-string NOR-based BCAM logic cells to make the corresponding vertical page in conduction state with the corresponding global bit line pulled to a low voltage level.

19. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 18 wherein the corresponding vertical page in non-conduction state is associated with a non-conduction state for each of the M 2T-string NOR-based BCAM logic cells wherein at least one of the first NAND flash transistor and the second NAND flash transistor is in non-conduction state.

20. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 18 wherein the corresponding vertical page in conduction state is associated with at least a conduction state for one of the M 2T-string NOR-based BCAM logic cells wherein both the first NAND flash transistor and the second NAND flash transistor are in conduction state.

21. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 11 wherein each of the M 2T-string NOR-based CAM logic cells is a 2T-string NOR-based Ternary CAM (TCAM) logic cell wherein at least one of the first NAND flash transistor and the second NAND flash transistor is further assigned with a third threshold voltage level Vt2 for defining a third CAM logic state “

X”

, the Vt2 level being selected to be a positive value greater than the VDD level based on Vt0<

VSS<

Vt1<

VDD<

Vt2.

22. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 21 wherein the third CAM logic state “

X”

is further associated with a physical state that both the first NAND flash transistor and the second NAND flash transistor in the 2T-string NOR-based TCAM logic cell are assigned with the third threshold voltage level Vt2 greater than the VDD level.

23. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 21 wherein the single logic-bit match is determined to be “

don'"'"'t care”

for the 2T-string NOR based TCAM logic cell at the third CAM logic state “

X”

wherein a non-conduction state is always associated with at least one of the first NAND flash transistor and the second NAND flash transistor no matter what the first word line and the second word line are respectively at either VSS=0V level or the complementary VDD level during the compare operation.

24. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 21 wherein the at least one M-bit match is found for one of the N vertical pages when all single logic-bit matches are found for each of the corresponding M 2T-string NOR-based TCAM logic cells at any one of the first CAM logic state “

0” and

the second CAM logic state “

1”

to make the corresponding vertical page in non-conduction state with the corresponding vertical global bit line stayed at a high voltage level, or not found when at least a no-match is found for one of the M 2T-string NOR-based TCAM logic cells to make the corresponding vertical page in conduction state with the corresponding vertical global bit line pulled to a low voltage level.

25. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 21 wherein a partial match is found for one of the N vertical pages when a single logic-bit match is found for each of K number of logic cells among the corresponding M 2T-string NOR-based TCAM logic cells, K is an integer selected from 1 through M−

1, at any one of the first CAM logic state “

0” and

the second CAM logic state “

1” and

a single logic-bit match is determined as “

don'"'"'t care”

for each of rest M−

K number of logic cells among the corresponding M 2T-string NOR-based TCAM logic cells at the third CAM logic state “

X”

to make the corresponding vertical page in non-conduction state with the corresponding vertical global bit line stayed at a high voltage level.

26. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 25 wherein the multiple matches found respectively for corresponding multiple vertical pages comprise

one or more partial matches respectively associated with one or more vertical pages within the corresponding multiple vertical pages wherein for each vertical page a single logic-bit match is found for each of K number of logic cells among the corresponding M 2T-string NOR-based TCAM memory cells at any one of the first CAM logic state “

0” and

the second CAM logic state “

1”

, K being an integer selected from 1 through M−

1, and a single logic-bit match is determined as “

don'"'"'t care”

for each of M−

K number of logic cells among the corresponding M 2T-string NOR-based TCAM logic cells at the third CAM logic state “

X”

to make the corresponding vertical page in non-conduction state with the corresponding vertical global bit line stayed at a high voltage level, and

at least one M-bit match for one vertical page among the corresponding multiple vertical pages wherein single-bit matches are found for all the corresponding M 2T-string NOR-based TCAM logic cells at any one of the first CAM logic state “

0” and

the second CAM logic state “

1”

to make the corresponding vertical page in non-conduction state with the corresponding vertical global bit line stayed at a high voltage level.

27. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 11 wherein the M 2T-string NOR-based CAM logic cells for each of the N vertical pages are arranged by

K number of 2T-string NOR-based BCAM logic cells each including a first NAND flash transistor and a second NAND flash transistor connected in series, K being one integer selected from 0 through M, wherein each of the first NAND flash transistor and the second NAND flash transistor being assigned a first threshold voltage level Vt0 and a second threshold voltage level Vt1 that are selected based on Vt0<

VSS<

Vt1<

VDD, and

M−

K number of 2T-string NOR-based TCAM logic cells each including a third NAND flash transistor and a fourth NAND flash transistor connected in series, wherein at least one of the third NAND flash transistor and the fourth NAND flash transistor being assigned the first threshold voltage level Vt0 and the second threshold voltage level Vt1 and further with a third threshold voltage level Vt2 that are selected based on Vt0<

VSS<

Vt1<

VDD<

Vt2.

28. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 27 wherein each of the K 2T-string NOR-based BCAM logic cells and each of the M−

K 2T-string NOR-based TCAM logic cells have the same number of NAND flash transistors.

29. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 27 wherein the K 2T-string NOR-based BCAM logic cells and the M−

K 2T-string NOR-based TCAM logic cells are arbitrarily arranged in the corresponding one of the N vertical pages.

30. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 27 wherein each pair of the M paired horizontal word lines are respectively assigned to either the ground voltage level VSS of 0V or the complementary level VDD without need of any WL voltage booster.

31. The sector of M×

N 2T-string NOR-based CAM logic cell array of claim 11 wherein the search word device comprises a SRAM-based data register for converting every 2 bits physical input data to a 1-bit logic word input following a FIFO I/O mechanism have a depth of at least two and providing to select gate signal for initiating the compare operation between the M logic-bits word page to stored word page in the selected one of the N vertical pages.