DIGITAL SIGNAL UP-CONVERTING APPARATUS AND RELATED DIGITAL SIGNAL UP-CONVERTING METHOD

• US 20140348279A1
• Filed: 05/09/2014
• Published: 11/27/2014
• Est. Priority Date: 05/21/2013
• Status: Active Grant

• Current Assignee: Xueshan Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: MediaTek, Inc.
• Inventors: Chen, Yang-Chuan, Wang, Chi-Hsueh, Chang, Hsiang-Hui, Lin, Bo-Yu
• Granted Patent: US 9,577,638 B2
• Time in Patent Office: Days
• US Class Current: 375/355
• CPC Class Codes: G01R 21/06 by measuring current and voltage G01R21/08 - G01R21/133 take precedence
• CPC Class Codes: G01R 23/00 Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/24 in discharge-tube amplifiers
• CPC Class Codes: H03F 2203/21154 An output signal of a power amplifier being controlled by controlling voltage signal
• CPC Class Codes: H03F 3/2178 using more than one switch or switching amplifier in parallel or in series H03F3/2173, H03F3/2175 take precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 19/017581 programmable
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H04B 1/04 Circuits
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 2001/0408 with power amplifiers
• CPC Class Codes: H04B 2001/045 with means for improving efficiency
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 27/2053 using more than one carrier, e.g. carriers with different phases
• CPC Class Codes: H04L 27/2067 with more than two phase states H04L27/2064 takes precedence
• CPC Class Codes: H04L 27/3411 reducing the peak to average power ratio or the mean power of the constellation; Arrangements for increasing the shape gain of a signal set
• CPC Class Codes: H04L 27/3444 by applying a certain rotation to regular constellations
• CPC Class Codes: H04L 7/0037 : Delay of clock signal
• CPC Class Codes: H04L 7/0091 : Transmitter details
• CPC Class Codes: H04W 24/02 : Arrangements for optimising operational condition

Abstract

A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Claims

1. A digital signal up-converting apparatus, comprising:

a clock generating circuit, arranged to generate a reference clock signal;

an adjusting circuit, coupled to the clock generating circuit, arranged to generate a first clock signal and a second clock signal according to the reference clock signal;

a baseband circuit, coupled to the adjusting circuit, for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and

a sampling circuit, coupled to the adjusting circuit and the baseband circuit, for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping;

wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

2. The digital signal up-converting apparatus of claim 1, wherein the first clock signal is a phase-adjusted clock signal of the reference clock and the second clock signal is a duty cycle-adjusted clock signal of the reference clock.

3. The digital signal up-converting apparatus of claim 1, further comprising:

an amplifier, arranged to generate an amplified output signal according to the combined digital signal.

4. The digital signal up-converting apparatus of claim 1, wherein the adjusting circuit comprises:

a phase adjusting circuit, arranged to adjust a phase of the reference clock to generate the first clock signal; and

a duty cycle adjusting circuit, arranged to adjust a duty cycle of the reference clock to generate the second clock signal.

5. The digital signal up-converting apparatus of claim 1, wherein the baseband circuit is arranged to delay a baseband data to generate the digital output signal according to the first clock signal.

6. The digital signal up-converting apparatus of claim 1, wherein signal edges of the second clock signal and the digital output signal are non-overlapping.

7. A digital signal up-converting apparatus, comprising:

a clock generating circuit, arranged to generate a first reference clock signal, a second reference clock signal, a third reference clock signal, and a fourth reference clock signal;

a phase adjusting circuit, arranged to adjust the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal to generate a first adjusted clock signal, a second adjusted clock signal, a third adjusted clock signal, and a fourth adjusted clock signal;

a baseband circuit, arranged to generate a first digital output signal, a second digital output signal, a third digital output signal, and a fourth digital output signal according to a first baseband data, a second baseband data, the first adjusted clock signal, the second adjusted clock signal, the third adjusted clock signal, and the fourth adjusted clock signal; and

a sampling circuit, arranged to sample the first digital output signal, the second digital output signal, the third digital output signal, and the fourth digital output signal to generate a first sampled digital signal, a second sampled digital signal, a third sampled digital signal, and a fourth digital signal according to the first adjusted clock signal, the second adjusted clock signal, the third adjusted clock signal, and the fourth adjusted clock signal respectively.

8. The digital signal up-converting apparatus of claim 7, further comprising:

an amplifier, arranged to generate an amplified output signal according to the first sampled digital signal, the second sampled digital signal, the third sampled digital signal, and the fourth digital signal.

9. The digital signal up-converting apparatus of claim 8, wherein the sampling circuit further directly combines the first sampled digital signal, the second sampled digital signal, the third sampled digital signal, and the fourth sampled digital signal in time domain to generate a combined digital signal.

10. The digital signal up-converting apparatus of claim 9, wherein the amplifier amplifies the combined digital signal to generate the amplified output signal.

11. The digital signal up-converting apparatus of claim 7, wherein the phase adjusting circuit selects one of the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal to be the first adjusted clock signal according to a selecting signal, and orderly outputs the non-selected reference clock signals to be the second adjusted clock signal, the third adjusted clock signal, and the fourth adjusted clock signal respectively.

12. The digital signal up-converting apparatus of claim 11, wherein the selecting signal is set according to frequencies of the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal.

13. The digital signal up-converting apparatus of claim 7, wherein the baseband circuit comprises:

a processing circuit, arranged to generate a first digital data, a second digital data, a third digital data, and a fourth digital data according to the first baseband data and the second baseband data;

a retiming circuit, arranged to generate a retime window clock according to a baseband window clock of the first digital data, the second digital data, the third digital data, and the fourth digital data and one of the first adjusted clock signal, the second adjusted clock signal, the third adjusted clock signal, and the fourth adjusted clock signal;

a first window clock latching circuit, arranged to generate a plurality of first window clocks according to the retime window clock and the first adjusted clock signal;

a second window clock latching circuit, arranged to generate a plurality of second window clocks according to the retime window clock and the second adjusted clock signal;

a third window clock latching circuit, arranged to generate a plurality of third window clocks according to the retime window clock and the third adjusted clock signal;

a fourth window clock latching circuit, arranged to generate a plurality of fourth window clocks according to the retime window clock and the fourth adjusted clock signal;

a first data latching circuit, arranged to generate the first digital output signal according to the first digital data and the plurality of first window clocks;

a second data latching circuit, arranged to generate the second digital output signal according to the second digital data and the plurality of second window clocks;

a third data latching circuit, arranged to generate the third digital output signal according to the third digital data and the plurality of third window clocks; and

a fourth data latching circuit, arranged to generate the fourth digital output signal according to the fourth digital data and the plurality of fourth window clocks.

14. The digital signal up-converting apparatus of claim 13, wherein the first digital data is obtained by subtracting the second baseband data from the first baseband data, the second digital data is obtained by adding up the first baseband data and the second baseband data, the third digital data is the inverse of the first digital data, and the fourth digital data is the inverse of the second digital data.

15. The digital signal up-converting apparatus of claim 13, wherein the retiming circuit is a latching circuit arranged to latch the baseband window clock by using one of the first adjusted clock signal, the second adjusted clock signal, the third adjusted clock signal, and the fourth adjusted clock signal to generate the retime window clock.

16. The digital signal up-converting apparatus of claim 13, wherein the first window clock latching circuit is arranged to latch the retime window clock by using the first adjusted clock signal to generate the plurality of first window clocks, the second window clock latching circuit is arranged latch the retime window clock by using the second adjusted clock signal to generate the plurality of second window clocks, the third window clock latching circuit is arranged to latch the retime window clock by using the third adjusted clock signal to generate the plurality of third window clocks, and the fourth window clock latching circuit is arranged to latch the retime window clock by using the fourth adjusted clock signal to generate the plurality of fourth window clocks.

17. The digital signal up-converting apparatus of claim 13, wherein the first data latching circuit is arranged to latch the first digital data by using the plurality of first window clocks to generate the first digital output signal, the second data latching circuit is arranged to latch the second digital data by using the plurality of second window clocks to generate the second digital output signal, the third data latching circuit is arranged to latch the third digital data by using the plurality of third window clocks to generate the third digital output signal, and the fourth data latching circuit is arranged to latch the fourth digital data by using the plurality of fourth window clocks to generate the fourth digital output signal.

18. The digital signal up-converting apparatus of claim 8, further comprising:

a duty cycle adjusting circuit, arranged to generate a first sampling clock signal, a second sampling clock signal, a third sampling clock signal, and a fourth sampling clock signal according to the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal respectively.

19. The digital signal up-converting apparatus of claim 18, wherein the sampling circuit comprises:

a first pass gate, arranged to sample the first digital output signal to generate the first sampled digital signal according to the first sampling clock signal;

a second pass gate, arranged to sample the second digital output signal to generate the second sampled digital according to the second sampling clock signal;

a third pass gate, arranged to sample the third digital output signal to generate the third sampled digital according to the third sampling clock signal; and

a fourth pass gate, arranged to sample the fourth digital output signal to generate the fourth sampled digital according to the fourth sampling clock signal.

20. A digital signal up-converting method, comprising:

generating a first reference clock signal, a second reference clock signal, a third reference clock signal, and a fourth reference clock signal;

adjusting the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal to generate a first adjusted clock signal, a second adjusted clock signal, a third adjusted clock signal, and a fourth adjusted clock signal;

generating a first digital output signal, a second digital output signal, a third digital output signal, and a fourth digital output signal according to a first baseband data, a second baseband data, the first adjusted clock signal, the second adjusted clock signal, the third adjusted clock signal, and the fourth adjusted clock signal; and

sampling the first digital output signal, the second digital output signal, the third digital output signal, and the fourth digital output signal to generate a first sampled digital signal, a second sampled digital signal, a third sampled digital signal, and a fourth digital signal according to the first adjusted clock signal, the second adjusted clock signal, the third adjusted clock signal, and the fourth adjusted clock signal respectively.

21. The digital signal up-converting method of claim 20, further comprising:

generating an amplified output signal according to the first sampled digital signal, the second sampled digital signal, the third sampled digital signal, and the fourth digital signal.

22. The digital signal up-converting method of claim 21, wherein the step of sampling the first digital output signal, the second digital output signal, the third digital output signal, and the fourth digital output signal further comprises:

directly combining the first sampled digital signal, the second sampled digital signal, the third sampled digital signal, and the fourth sampled digital signal in time domain to generate a combined digital signal.

23. The digital signal up-converting method of claim 22, wherein the step of generating the amplified output signal comprises:

amplifying the combined digital signal to generate the amplified output signal.

24. The digital signal up-converting method of claim 20, wherein the step of generating the first digital output signal, the second digital output signal, the third digital output signal, and the fourth digital output signal comprises:

generating a first digital data, a second digital data, a third digital data, and a fourth digital data according to the first baseband data and the second baseband data;

generating a retime window clock according to a baseband window clock of the first digital data, the second digital data, the third digital data, and the fourth digital data, and one of the first adjusted clock signal, the second adjusted clock signal, the third adjusted clock signal, and the fourth adjusted clock signal;

generating a plurality of first window clocks according to the retime window clock and the first adjusted clock signal;

generating a plurality of second window clocks according to the retime window clock and the second adjusted clock signal;

generating a plurality of third window clocks according to the retime window clock and the third adjusted clock signal;

generating a plurality of fourth window clocks according to the retime window clock and the fourth adjusted clock signal;

generating the first digital output signal according to the first digital data and the plurality of first window clocks;

generating the second digital output signal according to the second digital data and the plurality of second window clocks;

generating the third digital output signal according to the third digital data and the plurality of third window clocks; and

generating the fourth digital output signal according to the fourth digital data and the plurality of fourth window clocks;

25. The digital signal up-converting method of claim 24, wherein the first digital data is obtained by subtracting the second baseband data from the first baseband data, the second digital data is obtained by adding up the first baseband data and the second baseband data, the third digital data is the inverse of the first digital data, and the fourth digital data is the inverse of the second digital data.

26. The digital signal up-converting method of claim 20, further comprising:

generate a first sampling clock signal, a second sampling clock signal, a third sampling clock signal, and a fourth sampling clock signal according to the first reference clock signal, the second reference clock signal, the third reference clock signal, and the fourth reference clock signal respectively.

27. The digital signal up-converting method of claim 26, wherein the step of sampling the first digital output signal, the second digital output signal, the third digital output signal, and the fourth digital output signal comprises:

sampling the first digital output signal to generate the first sampled digital signal according to the first sampling clock signal;

sampling the second digital output signal to generate the second sampled digital according to the second sampling clock signal;

sampling the third digital output signal to generate the third sampled digital according to the third sampling clock signal; and

sampling the fourth digital output signal to generate the fourth sampled digital according to the fourth sampling clock signal.