INTERNAL ELECTRICAL CONTACT FOR ENCLOSED MEMS DEVICES

• US 20140349434A1
• Filed: 08/11/2014
• Published: 11/27/2014
• Est. Priority Date: 01/30/2013
• Status: Active Grant

• Current Assignee: Invensense Incorporated (TDK Corporation)
• Original Assignee: Invensense Incorporated (TDK Corporation)
• Inventors: HUANG, Kegang, SHIN, Jongwoo, LIM, Martin, DANEMAN, Michael Julian, SEEGER, Joseph
• Granted Patent: US 8,945,969 B2
• Time in Patent Office: Days
• US Class Current: 438/51
• CPC Class Codes: B81B 2207/098 Arrangements not provided for in groups B81B2207/092 - B81B2207/097
• CPC Class Codes: B81B 7/0064 for protecting against electromagnetic or electrostatic interferences
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: B81C 2203/031 Anodic bondings

Abstract

A method of fabricating electrical connections in an integrated MEMS device is disclosed. The method comprises forming a MEMS wafer. Forming a MEMS wafer includes forming one cavity in a first semiconductor layer, bonding the first semiconductor layer to a second semiconductor layer with a dielectric layer disposed between the first semiconductor layer and the second semiconductor layer, and etching at least one via through the second semiconductor layer and the dielectric layer and depositing a conductive material on the second semiconductor layer and filling the at least one via. Forming a MEMS wafer also includes patterning and etching the conductive material to form one standoff and depositing a germanium layer on the conductive material, patterning and etching the germanium layer, and patterning and etching the second semiconductor layer to define one MEMS structure. The method also includes bonding the MEMS wafer to a base substrate.

Claims

1. A method of fabricating electrical connections in an integrated MEMS device comprising:

forming a MEMS substrate comprising;

depositing a dielectric layer on a handle layer;

patterning and etching the dielectric layer to form at least one via to the handle layer;

depositing a silicon layer on the dielectric layer and into the at least one via;

patterning and etching the silicon layer to define one or more MEMS structures;

etching the dielectric layer to release the MEMS structures; and

bonding the MEMS substrate to a base substrate.

2. The method of claim 1, further comprising depositing a conductive layer on the silicon layer.

3. The method of claim 2, wherein the conductive layer comprises germanium.

4. The method of claim 1, further comprising depositing conductive pads on the base substrate.

5. The method of claim 4, where in the bond is an eutectic bond between the germanium and the conductive pads.

6. The method of claim 1, further comprises patterning and etching the silicon layer to form at least one stand-off.

7. The method of claim 6, where in the standoff is bonded to the base substrate.

8. The method of claim 1, wherein the base substrate comprises one of a semiconductor substrate and a CMOS substrate.

9. The method of claim 1, wherein the bonding provide electrical connection between the handle layer and the base substrate via the device layer.