BROADCAST FOR A DISTRIBUTED SWITCH NETWORK

• US 20140351484A1
• Filed: 05/22/2013
• Published: 11/27/2014
• Est. Priority Date: 05/22/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: McGlone, Elizabeth A., Spach, Daniel R., Wollbrink, Curtis C., Freking, Ronald E.
• Granted Patent: US 9,292,462 B2
• Time in Patent Office: Days
• US Class Current: 710/314
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: H04L 49/10 characterised by the switching fabric construction

Abstract

Techniques for broadcasting a command in a distributed switch, at a first switch module within the distributed switch. Embodiments receive a request to reset a PCIe link for a first host device, the first host device connected to a plurality of downstream PCIe devices through the distributed switch. A routing table specifying a plurality of downstream switch modules, connected to the first switch modules by one or more ports of the first switch module, is identified. Embodiments suspend PCIe traffic for the first host device on the one or more ports of the first switch module. Broadcast messages are transmitted to the plurality of downstream switch modules, specifying a first reset operation. Upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, embodiments resume PCIe traffic for the first host device on the one or more ports.

Claims

1. A computer-readable storage memory containing a program that, when executed, performs an operation for broadcasting a command at a first switch module within a distributed switch, comprising:

receiving a first request to reset a PCIe link for a first host device, wherein the first host device is connected to a plurality of downstream PCIe devices through the distributed switch;

identifying a routing table specifying a plurality of downstream switch modules, connected to the first switch module by one or more ports of the first switch module;

suspending PCIe traffic for the first host device on the one or more ports of the first switch module;

transmitting a respective broadcast message to each of the plurality of downstream switch modules, specifying a first operation to be performed for resetting the PCIe link for the first host device; and

upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, resuming PCIe traffic for the first host device on the one or more ports.

2. The computer-readable storage memory of claim 1, the operation further comprising:

while the PCIe traffic for the first host device is suspended, storing incoming PCIe traffic from the first host device for the one or more ports in a buffer; and

upon resuming PCIe traffic for the first host device, transmitting the stored incoming PCIe traffic from the buffer to corresponding downstream switch modules in the plurality of downstream switch modules.

3. The computer-readable storage memory of claim 1, the operation further comprising:

receiving a second request to reset the PCIe link for the first host device; and

determining whether the second request is a higher priority request relative to the first request.

4. The computer-readable storage memory of claim 3, the operation further comprising:

upon determining that the second request is a higher priority request relative to the first request, and before the acknowledgement messages are received from all of the plurality of downstream switch modules;

disregarding any subsequently received acknowledgement messages pertaining to the transmitted broadcast messages specifying the first operation; and

transmitting a respective second broadcast message to each of the plurality of downstream switch modules, specifying a second operation to be performed for resetting the PCIe link for the first host device.

5. The computer-readable storage memory of claim 1, wherein PCIe traffic from a second host device continues to flow through the one or more ports, while the PCIe traffic from the first host device for the one or more ports is suspended.

6. The computer-readable storage memory of claim 1, the operation further comprising:

upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, performing an operation for discovering downstream switch modules to rebuild the routing table.

7. The computer-readable storage memory of claim 1, wherein the received acknowledgement messages originate from at least one of a downstream switch module and a peripheral device coupled to the downstream switch module.

8. The computer-readable storage memory of claim 1, wherein the transmitted broadcast message comprises a PCIe reset message.

9. A switch module within a distributed switch, comprising:

a processor;

a plurality of ports connected to a plurality of downstream switch modules within the distributed switch; and

a memory containing a program that, when executed by the processor, performs an operation for broadcasting a command within the distributed switch, comprising;

receiving a first request to reset a PCIe link for a first host device, wherein the first host device is connected to a plurality of downstream PCIe devices through the distributed switch;

identifying a routing table specifying the plurality of downstream switch modules, connected to the switch module by the plurality of ports;

suspending PCIe traffic for the first host device on the plurality of ports;

transmitting a respective broadcast message to each of the plurality of downstream switch modules, specifying a first operation to be performed for resetting the PCIe link for the first host device; and

upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, resuming PCIe traffic for the first host device on the plurality of ports.

10. The system of claim 9, the operation further comprising:

while the PCIe traffic for the first host device is suspended, storing incoming PCIe traffic from the first host device for the plurality of ports in a buffer; and

upon resuming PCIe traffic for the first host device, transmitting the stored incoming PCIe traffic from the buffer to corresponding downstream switch modules in the plurality of downstream switch modules.

11. The system of claim 9, the operation further comprising:

receiving a second request to reset the PCIe link for the first host device; and

determining whether the second request is a higher priority request relative to the first request.

12. The system of claim 11, the operation further comprising:

upon determining that the second request is a higher priority request relative to the first request, and before the acknowledgement messages are received from all of the plurality of downstream switch modules;

disregarding any subsequently received acknowledgement messages pertaining to the transmitted broadcast messages specifying the first operation; and

transmitting a respective second broadcast message to each of the plurality of downstream switch modules, specifying a second operation to be performed for resetting the PCIe link for the first host device.

13. The system of claim 9, wherein PCIe traffic from a second host device continues to flow through the one or more ports, while the PCIe traffic from the first host device for the plurality of ports is suspended.

14. The system of claim 9, the operation further comprising:

upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, performing an operation for discovering downstream switch modules to rebuild the routing table.

15. The system of claim 9, wherein the received acknowledgement messages originate from at least one of a downstream switch module and a peripheral device coupled to the downstream switch module.

16. The system of claim 9, wherein the transmitted broadcast message comprises a PCIe reset message.