Systems and Methods for Inter-cell Interference Mitigation in a Flash Memory

• US 20140351668A1
• Filed: 06/06/2013
• Published: 11/27/2014
• Est. Priority Date: 05/22/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Zhang, Fan, Li, Shu, Xiao, Jun, Xia, Haitao
• Granted Patent: US 9,235,469 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/00 Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C

Abstract

The present inventions are related to systems and methods for accessing data from a flash memory, and more particularly to systems and methods for inter-cell interference handling in a flash memory.

Claims

1. A data processing system, the data processing system comprising:

a soft information correction circuit operable to;

receive soft information corresponding to a series of voltage levels accessed from a block of memory cells;

calculate corrected soft information based upon the received soft information and a variance of the soft information.

2. The data processing system of claim 1, wherein the data processing system further comprises:

a data decoder circuit operable to apply a data decoding algorithm to the corrected soft information to yield a data output.

3. The data processing system of claim 2, wherein the data decoder circuit is a low density data decoder circuit.

4. The data processing system of claim 1, wherein calculating the corrected soft information is based at least in part on both the variance and a median of the soft information.

5. The data processing system of claim 4, wherein calculating the corrected soft information comprises:

calculating an offset reduced output based upon a combination of the variance and the median; and

calculating the corrected soft information based upon the offset reduced output and the median.

6. The data processing system of claim 4, wherein the variance includes a left side variance and a right side variance, and wherein calculating the corrected soft information comprises:

calculating an offset reduced output based upon a combination of the right side variance, the left side variance, and the median; and

calculating the corrected soft information based upon the offset reduced output and the median.

7. The data processing system of claim 1, wherein the soft information is a probability that the voltage levels accessed from a block of memory cells are correct.

8. The data processing system of claim 7, wherein the soft information is log likelihood information.

9. The data processing system of claim 1, wherein the system is implemented as an integrated circuit.

10. The data processing system of claim 1, wherein the data processing system is incorporated in a storage device comprising:

a block of flash memory cells, wherein the block of memory cells are a subset of the block of flash memory cells.

11. The data processing system of claim 10, wherein each of the flash memory cells are multi-bit memory cells.

12. The data processing system of claim 11, wherein the multi-bit memory cells are each capable of storing a voltage level representative of a number of bits, and wherein the number of bits is selected from a group consisting of:

two bits, and three bits.

13. A method for accessing information from a storage device, the method comprising:

receiving soft information corresponding to a series of voltage levels accessed from a block of flash memory cells;

calculating corrected soft information based upon the received soft information and a variance of the soft information; and

applying a data decoding algorithm to the corrected soft information to yield a data output.

14. The method of claim 13, wherein the data decoding algorithm is a low density parity check decoding algorithm.

15. The method of claim 13, wherein calculating the corrected soft information is based at least in part on both the variance and a median of the soft information.

16. The method of claim 15, wherein calculating the corrected soft information comprises:

calculating an offset reduced output based upon a combination of the variance and the median; and

calculating the corrected soft information based upon the offset reduced output and the median.

17. The method of claim 15, wherein the variance includes a left side variance and a right side variance, and wherein calculating the corrected soft information comprises:

calculating an offset reduced output based upon a combination of the right side variance, the left side variance, and the median; and

calculating the corrected soft information based upon the offset reduced output and the median.

18. The method of claim 13, wherein the soft information is a probability that the voltage levels accessed from a block of memory cells are correct.

19. The method of claim 18, wherein the soft information is log likelihood information.

20. A storage device, the storage device comprising:

a block of memory cells, wherein each of the memory cells is operable to store a voltage level representing two or more bits;

a soft information correction circuit operable to;

receive soft information corresponding to a series of voltage levels accessed from the memory cells;

calculate corrected soft information based upon the received soft information and a variance of the soft information; and

a data decoder circuit operable to apply a data decoding algorithm to the corrected soft information to yield a data output.