SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20140353678A1
• Filed: 08/02/2012
• Published: 12/04/2014
• Est. Priority Date: 03/16/2012
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Kawakami, Tsuyoshi, Hamada, Kenji, Ebihara, Kohei, Furukawa, Akihiko, Murakami, Yuji
• Granted Patent: US 9,536,942 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region. Impurities of the second conductivity type are implanted to the second electric field relaxation layers at a second surface density lower than the first surface density, widths of which becoming larger as apart from the active region.

Claims

1. A semiconductor device comprising:

an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type; and

a plurality of electric field relaxation layers disposed from an edge of said active region toward the outside so as to surround said active region, wherein

said plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, said first electric field relaxation layer and said second electric field relaxation layer adjacent to each other forming a set,

impurities of a second conductivity type are implanted to said first electric field relaxation layers at a first surface density, widths of said first electric field relaxation layers becoming smaller as apart from said active region,

impurities of the second conductivity type are implanted to said second electric field relaxation layers at a second surface density lower than said first surface density, widths of said second electric field relaxation layers becoming larger as apart from said active region, and

said plurality of electric field relaxation layers are disposed in order of said first electric field relaxation layer and said second electric field relaxation layer from said active region side.

2. The semiconductor device according to claim 1, wherein in said plurality of electric field relaxation layers, a change amount by which the widths of said first electric field relaxation layers become smaller coincides with a change amount by which the widths of said second electric field relaxation layers become larger.

3. The semiconductor device according to claim 1,

said active region being a first main electrode layer of the second conductivity type,

said semiconductor device further comprising a second main electrode layer of the first conductivity type formed in a main surface of said semiconductor layer on a side opposite to the side on which said active region is provided,

wherein said first main electrode layer, said second semiconductor layer, and said second main electrode layer form a PN junction diode.

4. The semiconductor device according to claim 1,

said active region being a first main electrode layer of the second conductivity type,

said semiconductor device further comprising:

a second main electrode layer of the second conductivity type formed, in a main surface of said semiconductor layer on the side on which said active region is provided, apart from said active region;

a well layer of the first conductivity type formed so as to surround said second main electrode layer;

a gate insulating film formed from above an edge on said first main electrode layer side of said second main electrode layer to above said well layer on the first main electrode layer side; and

a gate electrode formed on said gate insulating film, wherein

said plurality of electric field relaxation layers are disposed between said first main electrode layer and said well layer, and

said first main electrode layer, said second main electrode layer, said well layer, and said gate electrode form a lateral MOS transistor in which main current flows between said first main electrode layer and said second main electrode layer through said plurality of electric field relaxation layers.

5. The semiconductor device according to claim 1, further comprising a plurality of additional electric field relaxation layers provided so as to surround said plurality of electric field relaxation layers, wherein

said plurality of additional electric field relaxation layers include a plurality of non-implantation regions, to which impurities of the second conductivity type are not implanted, and a plurality of third electric field relaxation layers having the same conductivity type and the same surface density as those of said second electric field relaxation layers, said plurality of non-implantation regions and said plurality of third electric field relaxation layers being alternately disposed adjacent to each other, each of said non-implantation regions and each of said third electric field relaxation layers adjacent to each other forming a set,

said third electric field relaxation layers have widths becoming smaller as apart from said active region,

said non-implantation regions have widths becoming larger as apart from said active region, and

said plurality of additional electric field relaxation layers are disposed in order of said non-implantation region and said third electric field relaxation layer from said active region side.

6. The semiconductor device according to claim 5, wherein in said plurality of additional electric field relaxation layers, a change amount by which the widths of said third electric field relaxation layers become smaller coincides with a change amount by which the widths of said non-implantation regions become larger.

7. The semiconductor device according to claim 5, wherein

said active region is a Schottky region that forms a Schottky junction with a Schottky electrode, and

said Schottky electrode and said Schottky region form a Schottky barrier diode.

8. The semiconductor device according to claim 7, wherein said first electric field relaxation layer closest to said active region among said plurality of electric field relaxation layers is formed to extend up to a portion below an end of said Schottky electrode.

9. The semiconductor device according to claim 5, wherein

said active region is an impurity layer of the second conductivity type, and

said impurity layer has the same conductivity type and the same surface density as those of said first electric field relaxation layers.

10. The semiconductor device according to claim 1, wherein

said first surface density is 1.2 to 2 times RESURF condition determined by a material of said semiconductor layer, and

said second surface density is 0.3 to 0.6 times said RESURF condition.

11. The semiconductor device according to claim 5, wherein

said second surface density is 0.6 to 0.9 times RESURF condition determined by a material of said semiconductor layer, and

said first surface density is 1.5 to 2.5 times said second surface density.

12. The semiconductor device according to claim 1, wherein among said plurality of electric field relaxation layers, sets each including said first electric field relaxation layer and said second electric field relaxation layer have the same total width except for at least one of a set including said first electric field relaxation layer closest to said active region and a set including said second electric field relaxation layer farthest from said second active region.

13. The semiconductor device according to claim 5, wherein in said plurality of additional electric field relaxation layers, all sets have the same total width of said non-implantation region and said third electric field relaxation layer that form a set.

14. The semiconductor device according to claim 1, wherein said semiconductor layer is formed of a wide band-gap semiconductor.

15. A method of manufacturing said semiconductor device according to claim 1, comprising the steps of:

(a) forming a first implantation mask on said semiconductor layer, and ion-implanting impurities of the second conductivity type at said second surface density, to thereby form an impurity layer identical to said second electric field relaxation layers so as to extend in regions in which said first electric field relaxation layers are formed; and

(b) after said step (a), forming on said semiconductor layer, a second implantation mask that covers at least portions located above regions to serve as said second electric field relaxation layers, and ion-implanting impurities of the second conductivity type at a surface density that becomes said first surface density through addition to said second surface density, to thereby form said first electric field relaxation layers.

16. A method of manufacturing said semiconductor device according to claim 5, comprising the steps of:

(a) forming a first implantation mask on said semiconductor layer and ion-implanting impurities of the second conductivity type at said second surface density to form an impurity layer identical to said second electric field relaxation layers so as to extend in regions in which said first electric field relaxation layers are formed, and forming said third electric field relaxation layers to define said non-impurity regions; and

(b) after said step (a), forming on said semiconductor layer, a second implantation mask that covers at least portions located above regions to serve as said second electric field relaxation layers, portions located above said third electric field relaxation layers, and portions located above said non-implantation regions, and ion-implanting impurities of the second conductivity type at a surface density that becomes said first surface density through addition to said second surface density, to thereby form said first electric field relaxation layers.

17. The semiconductor device according to claim 1, wherein

said active region is a Schottky region that forms a Schottky junction with a Schottky electrode, and

said Schottky electrode and said Schottky region form a Schottky barrier diode.

18. The semiconductor device according to claim 17, wherein said first electric field relaxation layer closest to said active region among said plurality of electric field relaxation layers is formed to extend up to a portion below an end of said Schottky electrode.

19. The semiconductor device according to claim 1, wherein

said active region is an impurity layer of the second conductivity type, and

said impurity layer has the same conductivity type and the same surface density as those of said first electric field relaxation layers.