SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE DEVICE BY FORMING MONOCRYSTALLINE SEMICONDUCTOR LAYERS ON A DIELECTRIC LAYER OVER ISOLATION REGIONS

• US 20140353725A1
• Filed: 05/29/2013
• Published: 12/04/2014
• Est. Priority Date: 05/29/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Adkisson, James W., Jain, Vibhor, Liu, Qizhi, Pekarik, John J., Cheng, Peng, Kaushal, Vikas Kumar
• Granted Patent: US 9,029,229 B2
• Time in Patent Office: Days
• US Class Current: 257/197
• CPC Class Codes: H01L 29/66242 Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 29/737 Hetero-junction transistors
• CPC Class Codes: H01L 29/7371 Vertical transistors

Abstract

Disclosed are devices and methods of forming the devices wherein pair(s) of first openings are formed through a dielectric layer and a first semiconductor layer into a substrate and, within the substrate, the first openings of each pair are expanded laterally and merged to form a corresponding trench. Dielectric material is deposited, filling the upper portions of the first openings and creating trench isolation region(s). A second semiconductor layer is deposited and second opening(s) are formed through the second semiconductor and dielectric layers, exposing monocrystalline portion(s) of the first semiconductor layer between the each pair of first openings. A third semiconductor layer is epitaxially deposited with a polycrystalline section on the second semiconductor layer and monocrystalline section(s) on the exposed monocrystalline portion(s) of the first semiconductor layer. A crystallization anneal is performed and a device (e.g., a bipolar device) is formed incorporating the resulting monocrystalline second and third semiconductor layers.

Claims

1. A method comprising:

forming a pair of first openings extending vertically through a sacrificial layer, a dielectric layer, and a first semiconductor layer and into a semiconductor substrate;

performing an etch process that laterally expands and merges said first openings within said semiconductor substrate only so as to create a trench;

depositing dielectric material on said sacrificial layer to fill upper portions of said first openings above said trench, thereby creating a trench isolation region;

removing said sacrificial layer;

forming a second semiconductor layer on said dielectric layer, said second semiconductor layer being any one of amorphous and polycrystalline;

forming a second opening extending vertically through said second semiconductor layer and said dielectric layer to expose a monocrystalline portion of said first semiconductor layer between said first openings; and

epitaxially depositing a third semiconductor layer on said second semiconductor layer and in said second opening such that said third semiconductor layer has polycrystalline section on said second semiconductor layer and a monocrystalline section on said monocrystalline portion of said first semiconductor layer in said second opening.

2. The method of claim 1, after said epitaxially depositing of said third semiconductor layer, performing an anneal to crystallize regions of both said second semiconductor layer and said polycrystalline section of said third semiconductor layer adjacent to said monocrystalline section of said third semiconductor layer.

3. The method of claim 1, said depositing of said dielectric material being performed so that an air gap is created within said trench as said upper portions of said first openings are filled.

4. The method of claim 1, said etch process comprising a crystallographic etch process.

5. The method of claim 1, said forming of said second opening comprising:

lithographically patterning and etching said second opening to expose said dielectric layer; and

performing a pre-cleaning process to expose said monocrystalline portion of said first semiconductor layer between said first openings.

6. A method of forming a bipolar device, said method comprising:

forming at least two pairs of first openings extending vertically through a sacrificial layer, a dielectric layer and an intrinsic base layer into a semiconductor substrate such that one pair of said first openings is on one side of a collector region in said semiconductor substrate and another pair of said first openings is on an opposite side of said collector region;

performing an etch process that laterally expands and merges said first openings of each of said pairs within said semiconductor substrate only so as to create trenches on opposing sides of said collector region;

depositing dielectric material on said sacrificial layer to fill upper portions of said first openings above said trenches to create trench isolation regions;

removing said sacrificial layer;

forming a first extrinsic base layer on said dielectric layer, said first extrinsic base layer being any one of amorphous and polycrystalline;

forming second openings extending vertically through said first extrinsic base layer and said dielectric layer so as to expose monocrystalline portions of said intrinsic base layer between said first openings of each of said pairs;

epitaxially depositing a second extrinsic base layer on said first extrinsic base layer and on said monocrystalline portions of said intrinsic base layer in said second openings such that said second extrinsic base layer has a polycrystalline section on said first extrinsic base layer and monocrystalline sections on said monocrystalline portions of said intrinsic base layer in said second openings.

7. The method of claim 6, further comprising, after said epitaxially depositing of said second extrinsic base layer, performing an anneal to crystallize regions of both said first extrinsic base layer and said polycrystalline section of said second extrinsic base layer adjacent to said monocrystalline of said second extrinsic base layer.

8. The method of claim 6, further comprising:

etching a third opening through said second extrinsic base layer and said first extrinsic base layer to said dielectric layer, said third opening be aligned above said collector region;

extending said third opening through said dielectric layer to said intrinsic base layer using a wet etch process such that a lower portion of said third opening undercuts said first extrinsic base layer; and

performing a selective epitaxial deposition process to form an additional semiconductor layer in said third opening,

said additional semiconductor layer filling said lower portion of said third opening such that an edge portion of said additional semiconductor layer is stacked vertically between a top surface of said intrinsic base layer and a bottom surface of said first extrinsic base layer,

said additional semiconductor layer further having a vertical extension positioned laterally adjacent to aligned vertical sidewalls of said first extrinsic base layer and said second extrinsic base layer above said lower portion of said third opening.

9. The method of claim 8, said edge portion and said vertical extension of said additional semiconductor layer creating an entirely monocrystalline link-up region between said intrinsic base layer and said first extrinsic base layer and said second extrinsic base layer.

10. The method of claim 8, further comprising forming an emitter layer in said third opening on said additional semiconductor layer.

11. The method of claim 6, said depositing of said dielectric material being performed so that an air gap is created within each of said trenches as said upper portions of said first openings of each of said pairs are filled.

12. The method of claim 6, said etch process comprising a crystallographic etch process.

13. The method of claim 6, said forming of said second openings comprising:

lithographically patterning and etching each of said second openings so as to initially expose said dielectric layer; and

performing a pre-cleaning process to expose said monocrystalline portions of said intrinsic base layer between said first openings of each of said pairs.

14. A bipolar device comprising:

a semiconductor substrate comprising trench isolation regions and a collector region positioned laterally between said trench isolation regions;

an intrinsic base layer on said semiconductor substrate above said collector region and extending laterally onto said trench isolation regions;

a dielectric layer on said intrinsic base layer;

pairs of first openings extending vertically through said dielectric layer and said intrinsic base layer, each pair being aligned above a trench isolation region and being filled with dielectric material;

a first extrinsic base layer on said dielectric layer;

second openings extending vertically through said first extrinsic base layer and said dielectric layer to monocrystalline portions of said intrinsic base layer between said first openings of each of said pairs; and

a second extrinsic base layer on said first extrinsic base layer and on said monocrystalline portions of said intrinsic base layer within said second openings.

15. The bipolar device of claim 14, said first extrinsic base layer and said second extrinsic base layer being monocrystalline.

16. The bipolar device of claim 14, further comprising:

a third opening extending vertically through said second extrinsic base layer, said first extrinsic base layer and said dielectric layer to said intrinsic base layer and being aligned above said collector region, said third opening having a lower portion within said dielectric layer that undercuts said first extrinsic base layer; and

an additional semiconductor layer filling said lower portion of said third opening such that an edge portion of said additional semiconductor layer is stacked vertically between a top surface of said intrinsic base layer and a bottom surface of said first extrinsic base layer, said additional semiconductor layer further having a vertical extension positioned laterally adjacent to aligned vertical sidewalls of said first extrinsic base layer and said second extrinsic base layer above said lower portion of said third opening.

17. The bipolar device of claim 16, said edge portion and said vertical extension of said additional semiconductor layer creating an entirely monocrystalline link-up region between said intrinsic base layer and said first extrinsic base layer and said second extrinsic base layer.

18. The bipolar device of claim 16, further comprising an emitter layer within said third opening on said additional semiconductor layer.

19. The bipolar device of claim 14, each trench isolation region comprising a trench with angled sidewalls.

20. The bipolar device of claim 14, each trench isolation region further comprising an air gap.