Tuning Strain in Semiconductor Devices

• US 20140353731A1
• Filed: 05/30/2013
• Published: 12/04/2014
• Est. Priority Date: 05/30/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Colinge, Jean-Pierre, Ching, Kuo-Cheng, Chang, Gwan Sin, Wu, Zhiqiang, Wang, Chih-Hao, Diaz, Carlos H.
• Granted Patent: US 9,006,842 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/02142 the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric.

Claims

1. A device comprising:

a substrate; and

a Fin Field-Effect Transistor (FinFET) comprising;

a semiconductor layer over the substrate, wherein the semiconductor layer forms a channel of the FinFET;

a first silicon germanium oxide layer over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage;

a second silicon germanium oxide layer over the first silicon germanium oxide layer, wherein the second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage;

a gate dielectric on sidewalls and a top surface of the semiconductor layer; and

a gate electrode over the gate dielectric.

2. The device of claim 1, wherein the first silicon germanium oxide layer has a first width, and wherein the second silicon germanium oxide layer has a second width smaller than the first width.

3. The device of claim 1, wherein the gate dielectric comprises a portion underlying, and in contact with, a bottom surface of the semiconductor layer.

4. The device of claim 1, wherein the first silicon germanium oxide layer and the second silicon germanium oxide layer have widths greater than a respective width of the semiconductor layer, with the widths of the first silicon germanium oxide layer and the second silicon germanium oxide layer and the width of the semiconductor layer being measured in a channel width direction of the FinFET.

5. The device of claim 4, wherein edges of the first silicon germanium oxide layer, the second silicon germanium oxide layer, and the semiconductor layer are substantially straight and vertical.

6. The device of claim 1, wherein the gate dielectric extends on sidewalls of the first and the second silicon germanium oxide layers.

7. The device of claim 1, wherein the semiconductor layer comprises silicon, and is substantially free from germanium.

8. A device comprising:

a substrate; and

a Fin Field-Effect Transistor (FinFET) comprising;

a first silicon germanium oxide layer over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage, and wherein the first silicon germanium oxide layer has a first width;

a second silicon germanium oxide layer over the first silicon germanium oxide layer, wherein the second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage, and wherein the second silicon germanium oxide layer has a second width smaller than the first width, with the first width and the second width being measured in a channel width direction of the FinFET;

a silicon layer over the second silicon germanium oxide layer, wherein the silicon layer forms a channel of the FinFET;

a gate dielectric on sidewalls and a top surface of the silicon layer; and

a gate electrode over the gate dielectric.

9. The device of claim 8, wherein the silicon layer comprises first edges on opposite sides of the silicon layer, wherein the first silicon germanium oxide layer comprises second edges on opposite sides of the first silicon germanium oxide layer, and wherein the second edges are recessed toward a center line of the silicon layer from the first edges.

10. The device of claim 8 further comprising Shallow Trench Isolation (STI) regions extending into the substrate, wherein the second silicon germanium oxide layer comprises:

a first portion over top surfaces of the STI regions; and

a second portion between opposite portions of the STI regions and lower than the top surfaces of the STI regions.

11. The device of claim 10, wherein the second portion of the second silicon germanium oxide layer has a width smaller than a width of the first portion of the second silicon germanium oxide layer.

12. The device of claim 8, wherein the gate dielectric comprises a portion underlying, and in contact with, a bottom surface of the silicon layer.

13. The device of claim 8, wherein the gate dielectric extends on sidewalls of the first silicon germanium oxide layer and the second silicon germanium oxide layer.

14. The device of claim 8, wherein the silicon layer is substantially free from germanium.

15. A method comprising:

performing a first epitaxy to form a first silicon germanium layer over a substrate;

performing a second epitaxy to form a second silicon germanium layer over the first silicon germanium layer;

performing a third epitaxy to form a silicon layer substantially free from germanium over the second silicon germanium layer;

oxidizing the first silicon germanium layer to form a first silicon germanium oxide layer;

forming a gate dielectric on a top surface and sidewalls of the silicon layer, wherein the gate dielectric extends on sidewalls of the first silicon germanium oxide layer; and

forming a gate electrode over the gate dielectric.

16. The method of claim 15 further comprising:

before the step of oxidizing, etching the first silicon germanium layer and the second silicon germanium layer, wherein after the step of etching, each of the first silicon germanium layer and the second silicon germanium layer comprises a remaining portion, and wherein the remaining portion of the second silicon germanium layer is narrower than the remaining portion of the first silicon germanium layer.

17. The method of claim 15 further comprising:

before the step of oxidizing, etching the first silicon germanium layer and the second silicon germanium layer, wherein after the step of etching, an entirety of the second silicon germanium layer is etched to form a gap.

18. The method of claim 17, wherein after the step of oxidizing, an entirety of the first silicon germanium layer is oxidized.

19. The method of claim 17, wherein after the step of oxidizing, outer portions of the first silicon germanium layer are oxidized, and an inner portion of the first silicon germanium layer is un-oxidized.

20. The method of claim 15, wherein in the step of oxidizing, a second silicon germanium oxide layer is generated from oxidized second silicon germanium layer, and wherein the method further comprises:

after the step of oxidizing, performing an annealing at an anneal temperature, wherein the anneal temperature is higher than a softening temperature of the second silicon germanium oxide layer, and lower than a softening temperature of silicon oxide.