WAFER-LEVEL PACKAGING OF INTEGRATED DEVICES, AND MANUFACTURING METHOD THEREOF

• US 20140353775A1
• Filed: 05/27/2014
• Published: 12/04/2014
• Est. Priority Date: 05/31/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV), STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Formosa, Kevin, Maggi, Luca
• Granted Patent: US 9,446,943 B2
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 2207/095 through the lid
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81B 3/0094 Constitution or structural means for improving or controlling physical properties not provided for in B81B3/0067 - B81B3/0091
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/00 Forming microstructural systems
• CPC Class Codes: B81C 2203/0136 Growing or depositing of a covering layer
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/84 : controllable by variation of applied mechanical force, e.g. of pressure
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A wafer-level packaging, comprising: a first semiconductor body integrating a MEMS structure; a second semiconductor body, including a surface electrical-contact region and an ASIC coupled to the MEMS structure and to said electrical-contact region; a first coating layer, made of resin, which englobes and protects the first body, the second body, and the electrical-contact region; at least one first conductive through via, which extends through the first coating layer in an area corresponding, and electrically coupled, to the first electrical-contact region; an electrical-contact pad, which extends over the first coating layer, electrically coupled to the first conductive through via; a third semiconductor body, integrating an electronic circuit, glued on the first coating layer; a second coating layer, made of resin, which englobes and protects the third body; at least one second conductive through via, which extends completely through the second coating layer in an area corresponding, and electrically coupled, to the electrical-contact pad; and a further electrical-contact pad electrically coupled to the second conductive through via.

Claims

1. A package comprising:

a first semiconductor body integrating a first microelectromechanical structure;

a second semiconductor body having a first side that includes;

an active region integrating an electronic circuit that is coupled to the first microelectromechanical structure; and

a first electrical-contact region operatively coupled to said electronic circuit;

a first coating layer of resin located over the first semiconductor body and the second semiconductor body and having a first surface;

a first conductive through via extending through the first coating layer and electrically coupled to the first electrical-contact region; and

a second electrical-contact region located on the first surface of the first coating layer and electrically coupled to the first conductive through via.

2. The package according to claim 1, further comprising:

a third semiconductor body integrating a second microelectromechanical structure;

a second coating layer of resin located between the second semiconductor body and the first coating layer and surrounding the third semiconductor body and the first electrical-contact region;

a second conductive through via that extends through the second coating layer and is electrically coupled to the first electrical-contact region; and

a third electrical-contact region located between the first coating layer and the second coating layer and is electrically coupled to the first conductive through via and to the second conductive through via.

3. The package according to claim 2, wherein the first semiconductor body includes a first electrical-contact pad operatively coupled to the first microelectromechanical structure,

said packaging further comprising:

a third conductive through via that extends through the first coating layer and is electrically coupled to the first electrical-contact pad; and

a fourth electrical-contact region located on the first surface of the first coating layer and is electrically coupled to the third conductive through via.

4. The package according to claim 2, wherein the first semiconductor body is coupled to the second coating layer by an adhesive layer.

5. The package according to claim 2, wherein the second semiconductor body includes a fourth electrical-contact region that is on the first side,

said packaging further comprising:

a third conductive through via that extends through the second coating layer and is electrically coupled to the second electrical-contact region; and

a first electrical-contact pad that is located between the first and second coating layers and is electrically coupled to the third conductive through via, wherein the first semiconductor body includes an active surface housing at least a second electrical-contact pad, said second electrical-contact pad of the first semiconductor body being electrically coupled to the first electrical-contact pad by a conductive wire.

6. The package according to claim 2, wherein the second semiconductor body includes a second electrical-contact region located on the first side, said packaging further comprising:

a third conductive through via that extends through the second coating layer and is electrically coupled to the second electrical-contact region;

a first electrical-contact pad located between the first and second coating layers and is electrically coupled to the third conductive through via; and

a solder ball, wherein the first semiconductor body includes an active surface housing a second electrical-contact pad, said second electrical-contact pad of the first semiconductor body being electrically coupled to the first electrical-contact pad by the solder ball.

7. The package according to claim 2, wherein said third semiconductor body is surrounded by said second coating layer and in direct contact with said second coating layer.

8. The package according to claim 1, wherein said first semiconductor body has side surfaces that are covered by said first coating layer and in direct contact with said first coating layer.

9. The package according to claim 1, further comprising:

a solder ball; and

a third semiconductor body that includes an active surface housing a first electrical-contact pad, said second semiconductor body housing a second electrical-contact pad, said third semiconductor body being electrically coupled to said second semiconductor body by flip-chip with the solder ball arranged between the first and the second electrical-contact pads.

10. The package according to claim 1, further comprising:

bonding wire; and

a third semiconductor body that includes an active surface housing a first electrical-contact pad, wherein said second semiconductor body houses a second electrical-contact pad,

wherein said third semiconductor body is electrically coupled to said second semiconductor body by the bonding wire coupled between the first and second electrical-contact pads.

11. The package according to claim 10, wherein the second semiconductor body further includes a redistribution layer that extends over the first side of the second semiconductor body, said redistribution layer forming an electrical-connection path between the first electrical-contact region and said second electrical-contact pad of the second semiconductor body.

12. An electronic apparatus comprising:

a printed circuit; and

a package that includes;

a first semiconductor body integrating a first microelectromechanical structure;

a second semiconductor body having a first surface that includes;

an active region integrating an electronic circuit; and

a first electrical-contact region that is electrically coupled to said first microelectromechanical structure and to said electronic circuit;

a molding compound located over the first semiconductor body and the second semiconductor body and having a first surface, the molding compound being in direct contact with the first semiconductor body;

a first conductive through via extending through the molding compound and coupled to the first electrical-contact region; and

a second electrical-contact region located on the first surface of the molding compound and coupled to the first conductive through via, wherein said package is operatively coupled to said printed circuit at the second electrical-contact region.

13. The electronic apparatus according to claim 12, wherein the electronic apparatus is at least one of a cellphone, a smartphone, a PDA, a tablet, a notebook, a voice recorder, an audio-file player, a console for videogames, a photographic camera, and a video camera.

14. The electronic apparatus according to claim 12, wherein the first semiconductor body is coupled to the second semiconductor body in a flip chip configuration and the molding compound abuts the first surface of the second semiconductor body.

15. A method comprising:

forming a first coating layer of resin above a first semiconductor body and a second semiconductor body, said first semiconductor body integrating a microelectromechanical structure, said second semiconductor body having a first side and integrating an electronic circuit, the first side of the second semiconductor body having a first electrical-contact region, said first coating layer having a first surface;

forming a first through hole in the first coating layer; and

forming a first conductive through via by filling the first through hole with conductive material; and

forming a second electrical-contact region on the first surface of the first coating layer, the second electrical-contact region being coupled to the first conductive through via.

16. The method according to claim 15, further comprising:

prior to forming the first coating layer;

coupling a third semiconductor body to the first side of the second semiconductor body;

forming a second coating layer of resin on the second semiconductor body covering surfaces of the third semiconductor body and the first electrical-contact region, said second coating layer having a second surface;

forming a second through hole by removing portions of the second coating layer exposing the first electrical-contact region;

forming a second conductive through via by filling the second through hole with conductive material, the second conductive through via being electrically coupled to the first electrical-contact region;

forming a third electrical-contact region on the second surface of the second coating layer and electrically coupled to the third electrical-cotnact region; and

wherein forming the first conductive through via includes forming the first through hole over the third electrical-contact region and filling the first through hole with conductive material to abut the third electrical-contact region.

17. The method according to claim 16, wherein the first semiconductor body houses a first conductive electrical-contact pad operatively coupled to the first microelectromechanical structure,

said method further comprising:

forming a third through hole by removing selective portions of the first coating layer in an area corresponding to the first conductive electrical-contact pad;

forming a third conductive through via by filling the third through hole with conductive material, the third conductive through via being electrically coupled to the first conductive electrical-contact pad; and

forming a fourth electrical-contact region on the first surface of the first coating layer, the fourth electrical-contact region being electrically coupled to the third conductive through via.

18. The method according to claim 16, further comprising mechanically coupling the first semiconductor body to the second surface of the second coating layer with an adhesive layer.

19. The method according to claim 16, wherein the second semiconductor body includes a second electrical-contact region, and the first semiconductor body includes an active surface housing a first electrical-contact pad,

said method further comprising:

forming a third through hole by removing selective portions of the second coating layer over the second electrical-contact region;

forming a third conductive through via by filling the third through hole with conductive material, the third conductive through via being electrically coupled to the second electrical-contact region;

forming a second electrical-contact pad over the third conductive through via and on the second surface of the second coating layer; and

coupling a first end of a conductive wire to said first electrical-contact pad of the third semiconductor body and a second end to the second electrical-contact pad.

20. The method according to claim 16, wherein the first side of the second semiconductor body includes a second electrical-contact region on the first side of the second body, and the first semiconductor body includes an active surface housing a first electrical-contact pad,

said method further comprising:

forming a third through hole by removing selective portions of the second coating layer in an area corresponding to the second electrical-contact region;

forming a third conductive through via by filling the third through hole with conductive material that is electrically coupled to the second electrical-contact region;

forming a second electrical-contact pad on the second surface of the second coating layer;

electrically coupling the second electrical-contact pad to the third conductive through via; and

electrically coupling, using a solder ball, said first electrical-contact pad to the second electrical-contact pad.

21. The method according to claim 15, wherein forming the first coating layer comprises:

forming said first coating layer in direct contact with said first semiconductor body; and

surrounding surfaces of said first semiconductor body with said second coating layer.

22. The method according to claim 16, wherein forming the second coating comprises:

forming said second coating in direct contact with said third semiconductor body and

surrounding surfaces of said third semiconductor body with said second coating layer.

23. The method according to claim 16, wherein said third semiconductor body includes an active surface housing a first electrical-contact pad, and said second semiconductor body houses a second electrical-contact pad, the method further comprising electrically coupling said third semiconductor body to said second semiconductor body by a solder ball interposed between the first and second electrical-contact pads.

24. The method according to claim 16, wherein said third semiconductor body includes an active surface housing a first electrical-contact pad, and said second semiconductor body houses a second electrical-contact pad, the method further comprising electrical wire coupled between the first and second electrical-contact pads.

25. The method according to claim 21, further comprising:

forming a routing layer in an area corresponding to the first side of the second semiconductor body; and

patterning said routing layer to form at least one electrical-connection path between the first electrical-contact region and said second electrical-contact pad of the second semiconductor body.

26. The method according to claim 15, wherein filling the first through hole includes injecting conductive material into said first through hole.