Digital PLL With Hybrid Phase/Frequency Detector and Digital Noise Cancellation

• US 20140354336A1
• Filed: 05/21/2014
• Published: 12/04/2014
• Est. Priority Date: 05/28/2013
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Syllaios, Ioannis Loukas, Jensen, Henrik Tholstrup
• Granted Patent: US 9,319,051 B2
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider

Abstract

Digital phase-locked loop (PLL) with dynamic hybrid (mixed analog/digital signal) delta-sigma (ΔΣ) phase/frequency detector (ΔΣ PFD). A hybrid 2nd-order ΔΣ PFD may be implemented based on a continuous-time 1st-order ΔΣ analog-to-digital converter (ADC) enhanced to 2nd-order via closed loop frequency detection. Fine resolution encoding of the ΔΣ PFD output facilitates true multi-bit phase/frequency error digitization with drastically reduced ΔΣ quantization noise. The implementation of low complexity ΔΣ PFD is assisted via digital requantization and adaptive noise cancellation. The PLL includes independent frequency-locking and phase-locking operational modes and all-digital control of a digitally controlled oscillator (DCO).

Claims

1. A phase locked-loop (PLL) comprising:

a digitally controlled oscillator (DCO) configured to generate a DCO output frequency in response to a tuning input;

a frequency reference oscillator configured to generate a reference frequency input;

a mixed analog/digital signal Delta-Sigma (Δ

Σ

) Phase/Frequency Detector (Δ

Σ

PFD) configured to generate a digital output of frequency difference between the reference frequency input and the DCO frequency output;

an accumulator configured to generate digital phase and frequency error information by accumulating the Δ

Σ

PFD digital output combined with a digital indicator of a targeted output frequency for the DCO;

a loop filter following the accumulator and configured to tune phase/frequency of the DCO in response to digital phase and frequency error information;

2. The PLL of claim 1, where the Δ

Σ

PFD comprises a phase and frequency detector including an analog to digital converter (ADC) for digitizing analog phase error and frequency error information.

3. The PLL of claim 2, where the ADC is configured to selectively operate in:

a fine resolution mode providing a fine mode number of quantization levels; and

a coarse resolution mode providing fewer quantization levels than the fine mode number of quantization levels.

4. The PLL of claim 3, where the coarse resolution mode provides at least two quantization levels and the fine resolution mode provides at least four quantization levels.

5. The PLL of claim 2, where the ADC comprises a Delta-Sigma (Δ

Σ

) ADC.

6. The PLL of claim 5, where the detector further comprises a charge-pump configured to drive the Δ

Σ

ADC.

7. The PLL of claim 6, where the detector further comprises a multi-modulus divider (MMD) configured to receive and divide the DCO output frequency.

8. The PLL of claim 7, where the detector further comprises a fine resolution encoder circuit configured to interface the Δ

Σ

ADC output to the MMD control input.

9. The PLL of claim 8, where the detector comprises a phase and frequency detector (PFD) charge-pump front-end driven by the reference frequency input and the feedback multi-modulus divider output.

10. The PLL of claim 9, where the PFD charge-pump front-end drives a Δ

Σ

ADC in communication with the fine resolution encoder.

11. The PLL of claim 1, where the detector comprises a Δ

Σ

ADC with digital requantizer for interfacing fine resolution analog-to-digital conversion to coarse resolution feedback digital-to-analog conversion.

12. The PLL of claim 1, where the detector comprises an adaptive filter configured to cancel noise affecting the detector.

13. A method comprising:

performing phase/frequency detection with respect to a reference frequency and a feedback signal;

generating a multiple bit error encoding of phase/frequency error responsive to the detection;

receiving the multiple bit error encoding at a loop filter; and

controlling a digitally controlled oscillator (DCO) with the loop filter to generate a reference frequency output.

14. The method of claim 13, further comprising:

generating the feedback signal by applying a multi-modulus divider (MMD) to the reference frequency output.

15. The method of claim 14, further comprising:

dithering the multiple bit error encoding to interface the MMD.

16. The method of claim 13, further comprising:

configuring an analog-to-digital converter (ADC) to act in a coarse resolution mode and in a fine resolution mode.

17. The method of claim 13, where generating the multiple bit error encoding comprises:

providing a digital requantization circuit between a fine resolution analog-to-digital conversion and a coarse resolution digital-to-analog conversion.

18. The method of claim 13, further comprising:

performing adaptive noise filtering and cancellation of noise affecting the phase/frequency detection.

19. A phase locked loop (PLL) comprising:

a reference frequency input;

a phase and frequency detector charge-pump in communication with the reference frequency input;

a delta sigma analog-to-digital converter (ADC) driven by the charge-pump, the ADC comprising a resolution mode input configured to selectively change the ADC between;

a fine resolution mode providing a fine mode number of quantization levels for phase and frequency error; and

a coarse resolution mode providing fewer quantization levels for the phase and frequency error than the fine mode number of quantization levels;

a loop filter following the ADC and configured to accept the phase and frequency error and responsively drive a digitally controlled oscillator (DCO) that generates a reference frequency output; and

a feedback path from the DCO to the charge-pump, the feedback path comprising a multi-modulus divider (MMD).

20. The PLL of claim 19, further comprising a dither circuit configured to interface the fine mode number of quantization levels to a lower-resolution MMD control grid of the MMD.